CCSDS AR4JA LDPC Decoder & Encoder

Overview

AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time. Pipeline architecture is followed which significantly speeds up the whole decoding process. Also, layered architecture is implemented which helps to enhance the speed of the decoding process. AR4JA LDPC decoder supports soft decision decoding and hard decision output.

AR4JA LDPC decoder uses Min-Sum algorithm to perform decoding. Min-Sum algorithm is an iterative algorithm that progresses to convergence through two updates: check node update, and variable node update. Check node update is evaluated by calculating the minimums and signs of all connected variable nodes. Then variable node update takes place. Processing is done layer by layer until all layers and iterations are completed.

Key Features

CCSDS AR4JA LDPC Code family is quasi-cyclic
Irregular parity check matrix
Run time configuration for more than one code rate (i.e., 1/2, 2/3, 3/4)
Configurable codeword size that supports 2K, 3K, and 4K information words;
Minimum sum algorithm;
Layered decoding architecture;
Soft decision decoding;
Configurable iteration number;
Synthesized on ASIC 40nm and Xilinx FPGA (Virtex-UltraScaleVCU 118)
Compatible with "LOW DENSITY PARITY CHECK CODES FOR USE IN NEAR-EARTH AND DEEP SPACE APPLICATIONS, CCSDS 131.1-O-2, September 2007" standard

Benefits

Due to rapid revolution in modern communication systems, specifically deep communication, adaptive data code rates are highly desired. That's because of the restriction of the latency and bandwidth in such medium. This means that system parameters need to be runtime configured based on the time-varying channel states and user requirements. To adjust the code rate according to the channel conditions, Rate-Compatible punctured Code (RCPC) is the optimal solution. Accordingly, Accumulate-Repeat-4-Jagged-Accumulate (AR4JA) Low-Density Parity-Check code (LDPC) is proposed. AR4JA LDPC code is irregular and quasi-cyclic code family. H-matrix of AR4JA LDPC code consists of sub-matrices that are padded, copied, and permutated in order to construct the various code rates. AR4JA LDPC code is characterized by faster convergence of bit-error rate (BER) with less number of iterations compared to quasi-cyclic codes. The implemented design supports code rates 1/2 (N=8192, K=4096), 2/3 (N=3072, K=2048) and code rate 3/4(N=4096, K=3072). Configurable number of iteration is carried out based on the target error correction performance. Two levels of parallelism are carried out that greatly enhance the decoding latency, check node parallelism and variable node parallelism. A trade-off exists among the design key parameters which are: code rate, decoding latency, power efficiency, throughput, and area.

Applications

CCSDS
Near Earth and Deep-Space communication
Space Links communication
Space Internet working services
FLASH Memory

Deliverables

Synthesizable Verilog
System model (Mat lab)
Verilog test bench
Comprehensive documentation

Technical Specifications

Maturity

silicon proven

Availability

immediately

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