The AXI MCDMA facilitates large data migration, offloading the task from the embedded processor. It sits as an intermediary between an AXI Memory-Mapped embedded subsystem an AXI Streaming subsystem.
The MCDMA IP is full-duplex, scatter-gather, and supports up to 16 channels. It may be configured as weighted round robin or strict priority.
AXI Multichannel DMA
Overview
Key Features
- 64-bit addressing
- Widths up to 1024 bits
- Scatter Gather Descriptors
- One Streaming interface, up to 16 Memory Mapped interfaces
- Full Duplex: Egress (Streaming to Memory Mapped) and Ingress (Memory Mapped to Streaming)
- Baremetal and Linux drivers
- Synchronous and Asynchronous clocking
Technical Specifications
Related IPs
- AXI Video DMA (AXI VDMA)
- AHB Multi-Channel DMA Controller
- AXI4 Multi-Channel DMA Controller
- Multi-channel DMA Controller
- DMA AXI4-Stream Interface to AXI Memory Map Address Space
- AXI / AHB / APB - SPI Flash Memory Controller - Octal/Quad/Dual/Single SPI I/O - CPU access to Flash and optional Execute-in-Place (XIP), Boot, DMA