So_ip_edte_un_s core can be used to implement the ensemble member evaluation module as a part of an ensemble classifier consisting from decision tree with the previously defined structure directly in hardware. It uses a single module with area efficient sequential architecture to implement every DT from the ensemble using. This architecture has the lowest possible resource usage therefore enabling the very efficient implementation of DT ensembles, while still having a fairly fast classification speed.
So_ip_edte_un_s core is delivered with fully automated testbench and a compete set of tests allowing easy package validation at each stage of SoC design flow.
The so_ip_edte_un_s design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset.
The so_ip_edte_un_s core can be evaluated using any evaluation platform available to the user before actual purchase. This is achieved by using a time-limited demonstration bit files for selected platform that allows the user to evaluate system performance under different usage scenarios.
Area-efficient decision tree ensemble evaluation core based on serial evaluation of ensemble members
Overview
Key Features
- Implements ensemble classifier comprised from DTs with previously defined structure
- All ensemble members are implemented using only one DT module with area efficient architecture, enabling lowest resource count possible when implementing DT ensemble in hardware
- Supports classification problems that are defined by numerical attributes only
- DTs with univariate or multivariate tests are supported
- DTs with nonlinear tests are supported
- Possibility to alter the implemented DT structure during the actual operation
- No special IP blocks are needed to implement the core, only memory, adders and multipliers
- User can specify the number format for all DT parameters in order to achieve the best performance/size ratio after implementation
Deliverables
- VHDL Source Code or netlis
- Verification environment with regression suite
- Technical documentation
- Installation notes
- User Manual
- Datasheet
- Instantiation templates
- Reference Design
- Technical Support
- IP Core implementation support
- Variable length maintenance
- Delivery of IP Core updates, minor and major changes
- Delivery of documentation updates
- Telephone & email support
Technical Specifications
Related IPs
- Area-efficient decision tree ensemble evaluation core based on parallel evaluation of ensemble members
- Decision tree ensemble evaluation core based on serial evaluation of ensemble members
- Decision tree ensemble evaluation core based on parallel evaluation of ensemble members
- Decision tree evaluation core using serial architecture
- Decision tree evaluation core using pipelined architecture
- Decision tree ensemble classifier inference core