40G UDPIP offload engine

Overview

The core Implements a UDP/IP hardware protocol stack that enables wire-speed communication over a LAN or a point-to-point connection. It is ideal for offloading the host processor from the demanding task of UDP/IP and can be used in both FPGA and ASIC designs.

Key Features

  • 40G Ethernet; IPv4 support;
  • Transmit and Receive; Five RX ports with 32 RXchannels and Five TX ports with 32TX channels supported;
  • ARP client/server with 32 entry ARP table;
  • ICMP (Ping Reply);
  • IGMP v3 membership Query/Report messaging;
  • UDP/IP Unicast and Multicast;
  • UDP Port Filtering;
  • 801.1Q tagging for VLAN support
  • UDP/IP Checksum calculation and validation
  • DHCP client
  • Flexible packet data interface with 128-bit and 64-bit data with configurable streaming capable using AXI4-Stream; Control/Status interface.

Benefits

  • Great reliability and high performance
  • Effectively offload CPU

Block Diagram

40G UDPIP offload engine Block Diagram

Applications

  • data center
  • video stream
  • data processing

Deliverables

  • 40G UDPIP Core netlist file
  • 40G MAC/PCS VHDL source
  • Reference design VHDL source
  • Testbench VHDL source

Technical Specifications

Maturity
fully verified on Xilinx and Altera FPGA devices
Availability
Aug. 2017
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