The PCI-M32 implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up to 33 MHz PCI clock.
The PCI-M32 Interface has both Master and Target capabilities. The interface implements 64 bytes of PCI Configuration Space registers. It is possible to extend the Configuration Space up to 256 bytes if required.
The Target part supports up to six Base Address Registers with both I/O and Memory space decoding from 16 bytes up to 2 GB. Both Target and Master supported commands are:
The PCI-M32 builds on more than 15 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.
