3.3V RTC Power On Reset; UMC 55nm uLP/SST Logic Process
Overview
3.3V RTC Power On Reset; UMC 55nm uLP/SST Logic Process
Technical Specifications
Foundry, Node
UMC 55nm eNVM EFLASH/EE2PROM/uLP-SPLIT_GATE
UMC
Pre-Silicon:
55nm
Related IPs
- BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.08-1.98V)
- Power On Reset
- On-Chip IO to Core Voltage Buck Regulator on UMC 55nm ULP
- BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=1.6-1.98V)
- BANDGAP POR & APC Advanced Power Controller with Power on Reset (Vin=2.3-3.6V)
- BANDGAP POR & APC Advanced Power Controller with ower on Reset (Vin=2.3-3.6V)