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DVB IP Core

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Search (81)
Compare 81 DVB IP Core from 21 vendors (1 - 10)
  • VHF/ UHF/L (DVB-H, DMB and ISDB-T) RF Front-end
    • TSMC BiCMOS SiGe 180 nm technology
    • Direct conversion receiver
    • A few number of external components
    • 0.18 um SiGe BiCMOS technology
    Block Diagram -- VHF/ UHF/L (DVB-H, DMB and ISDB-T) RF Front-end
  • DVB-RCS2 Multi-Carrier Receiver
    • Compliant with ETSI EN 301 545-2 (DVB-RCS2)
    • Support for Linear Modulation Bursts of Table A-1
    • Optional support for Spread-spectrum Linear Modulation Burst waveforms of Table A-2
    • Support for BPSK, QPSK, 8-PSK, 16-QAM
    Block Diagram -- DVB-RCS2 Multi-Carrier Receiver
  • DVB-S2X Demodulator
    • Compliant with DVB-S2 and DVB-S2X
    • Supports ACM, CCM, and VCM modes
    • Support for short and long blocks (16,200 bits and 64,800 bits)
    • Support for QPSK to 256-APSK
    Block Diagram -- DVB-S2X Demodulator
  • DVB-T/H Modulator
    • ETSI, DVB-T/H (EN 300 744 V1.5.1) Compliant baseband transmitter for Digital Terrestrial Television
    • · The MVD modulator cores can be delivered with an Intermediate Frequency output or a RF output when using Analog Devices or Maxim RF DACs (see separate datasheet, available on request)
    • · Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
    • · Single clock (up to 140 MHz+ for Spartan-3/6™, 180 MHz+ for Virtex-5/6™)
    Block Diagram -- DVB-T/H Modulator
  • Multistream DVB-S2 Modulator
    • Aggregation of up to 8 input streams
    • Complete user control to choose any number of streams
    • Each stream independently configurable
    • DVB-S2 CCM and VCM operations
    Block Diagram -- Multistream DVB-S2 Modulator
  • DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
    • Combines a configurable DVB-T2/T/C/S/S2 demodulator.
    • AGC derived from IF
    • Low-power process, design and architecture
    • Includes full suite of low-level drivers and application software, detailed user manuals and reference design schematics
    Block Diagram -- DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
  • Digital Video Broadcasting - (DVB-ASI) IP Core
    • Configurable Tx FIFO supporting independent Layer 2 transmit clock
    • Configurable Rx FIFO supporting independent Layer 2 receive clock
    • Automatic start of packet comma insertion in the transmit side
    • Rate-matching comma insertion in the transmit side
    Block Diagram -- Digital Video Broadcasting - (DVB-ASI) IP Core
  • ISO/IEC 21122-1 JPEG-XS Standard Codec
    • Support YUV444/ YUV422 input format
    • Support color depth: 8bit / 10bit(optional) /12 bit(optional).
    • Multi-Channel (optional)
    • Visual Lossless compression
    Block Diagram -- ISO/IEC 21122-1 JPEG-XS Standard Codec
  • DVB-C Demodulator IP (Silicon Proven)
    • QAM and FEC solution
    • ITU-T J.83 Annexes A/B/C, DVB-C specification (ETSI 300 429)
    • Nordig Unified v2.4 and SARFT compliant
    • Up to 7.2 Ms/s symbol rate
    Block Diagram -- DVB-C Demodulator IP (Silicon Proven)
  • DVB-T2/T Demodulator and Decoder IP (Silicon Proven)
    • DVB-T2 with T2-base profile of ETSI EN- 302755 v1.3.1,DTG7 v3 and Nordig Unified v2.4 compliant, 1.7-5-6-7 and 8 MHz normal and extended BW signals supported, GS streams, FEF and MISO supported
    • DVB-T demodulator: Compliant with ETSI EN-300744 v1.5.1, DTG7 v3 and Nordig Unified v2.4 compliant, 6-7 and 8 MHz BW supported
    • DVB-T/T2 compatible with zero-high- and legacy-IF tuners (CAN or silicon)
    • Embedded microcontroller (DVB-T2 task sequencing by firmware and monitoring)
    Block Diagram -- DVB-T2/T Demodulator and Decoder IP (Silicon Proven)
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