TSMC N3E IP
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69
IP
from 3 vendors
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10)
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eUSB 2.0 PHY - TSMC N3E x1, North/South (vertical) poly orientation
- Designed for 7nm processes and below
- Supports the USB 2.0 protocol and High Speed, Full Speed, and Low Speed data rates
- eUSB2 PHYs supports USB 2.0, 3.0, 3.1 and 3.2 Device, Host and Dual Role configurations
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10G PHY for Differential Buffer, TSMC N3E, North/South (vertical) poly orientation
- Compliant with the PCI Express (PCIe®) 3.1, 2.1, 1.1 and PIPE specifications
- x1, x2, x4, x8, x16 lane configurations with bifurcation
- Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
- L1 substate and SRIS support
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MIPI MPHY Type 1 G4 2TX2RX - TSMC N3E 1.2V, North/South Poly Orientation
- Compliant with MIPI M-PHY v5.0 specification
- Supports MIPI UniPro, JEDEC UFS protocols
- Supports High-Speed (HS) Gear1,
- Gear2, Gear3, Gear4 and Gear5 A/B modes
- Supports M-PHY Type-I
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MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes - TSMC N3E 1.2V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
- Compliant with the MIPI C-PHY specification, v2.0
- 3 trios in C-PHY mode up to 6.5Gs/s per trio
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MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes -TSMC N3E 1.2V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
- Compliant with the MIPI C-PHY specification, v2.0
- 3 trios in C-PHY mode up to 6.5Gs/s per trio
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MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes - TSMC N3E 1.2V, North/South Poly Orientation
- Compliant with the MIPI D-PHY specification, v2.1
- 4 Lanes in D-PHY mode up to 6.5Gb/s per lane
- Compliant with the MIPI C-PHY specification, v2.0
- 3 trios in C-PHY mode up to 6.5Gs/s per trio
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HDMI 2.1/ DispalyPort 2.1 Tx PHY TSMC N3E 1.2V, North/South Poly Orientation
- HDMI 2.1 TX IP solution includes PHYs, controllers, HDCP embedded security modules, and verification IP
- Compliant with the HDMI 2.1, 2.0, 1.4, and HDCP 2.3, 1.4 specifications
- Support for key HDMI 2.1 features such as fixed-rate link capable of 48Gbps aggregate bandwidth, enhanced
- Metadata packets including dynamic HDR, eARC, auto low-latency mode, and variable refresh rate
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HDMI 2.1 Tx PHY TSMC N3E 1.2V, North/South Poly Orientation
- HDMI 2.1 TX IP solution includes PHYs, controllers, HDCP embedded security modules, and verification IP
- Compliant with the HDMI 2.1, 2.0, 1.4, and HDCP 2.3, 1.4 specifications
- Support for key HDMI 2.1 features such as fixed-rate link capable of 48Gbps aggregate bandwidth, enhanced
- Metadata packets including dynamic HDR, eARC, auto low-latency mode, and variable refresh rate
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UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation
- Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
- Compliant with the latest UCIe specification
- Integrated signal integrity monitors and comprehensive test and repair features
- Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout
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HBM3 PHY V2 - TSMC N3E
- Supports 2.5D-based JEDEC standard HBM3 DRAMs with data rates up to 9600 Mbps
- 16 independent 64-bit memory channels
- Pseudo-channel operation supported to enable up to 32 32-bit pseudo-channels with 1024-bit PHY
- Supports up to 4 trained frequencies with <5us switching time
