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TSMC 3nm IP

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Compare 86 IP from 7 vendors (1 - 10)
  • Fractional-N Frequency Synthesizer PLL
    • Wide functional range allows all frequencies in a system to be synthesized with one PLL macro
    • Input & output frequency ranges greater than 1000:1
    Block Diagram -- Fractional-N Frequency Synthesizer PLL
  • TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks
    • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
    • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
    • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
    • Supports retention and bus-keeper feature
  • TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries
    • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
    • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
    • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
    • Supports retention and bus-keeper feature
  • TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
    • Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
    • Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
    • Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
    • Supports retention and bus-keeper feature
  • TSMC 3nm (N3E) 1.2V LVDS Tx/Rx with 1.8V BGR
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • TSMC 3nm (N3E) 1.5V LVDS
    • Maximum operating speed: up to 3.4GBPS
    • Compatibility with TIA/EIA - 644-A for greater interoperability
    • Loop back option supported for both Pre/Post driver in LVDS TX
    • HBM 2KV, CDM 500V (up to 7A)
  • TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
  • TSMC 3nm (N3E) 1.8V SD/eMMC IO
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
  • TSMC 3nm (N3E) 1.8V SD/eMMC PHY
    • Completely hardened PHY solution along with programmable delay chains & I/Os
    • Fully selectable output impedance
    • Compliant with eMMC 5.1 (JESD84-B51A) and SDIO 3.0 JEDEC Standard
    • Automotive G1/G2 supported, ASIL-B certified
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