Tsmc 3nm IP

003TSMC_PVT_01 IP library is a unique solution intended to continuously monitor IC status at several on-die locations.
It is able to detect manufacturing process deviation, perform voltage, current and die temperature measurement.

Fractional-N Phase locked loop frequency synthesizer is intended for ASIC clock generation.
The Fractional-N PLL loop with 2GHz-4GHz VCO has high phase noise performance and ultra-fine frequency tuning step.
VCO Sub-band auto select (SAS) system allows to find automatically appropriate sub-band for VCO on locked PLL.

New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.
Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.
Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.
Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.

Designed for PC, networking, and consumer-electronics applications where spread-spectrum clock sources are required to satisfy FCC requirements for peak RF spectral emissions.
Spreading rate and spreading depth are precisely adjustable to allow the designer to dial-in the desired characteristics.
15-bit fractional-N feedback divider with 4 bits of precise control.
Available with multi-phase outputs.

Designed for PC, networking, and consumer-electronics applications where spread-spectrum clock sources are required to satisfy FCC requirements for peak RF spectral emissions.
Spreading rate and spreading depth are precisely adjustable to allow the designer to dial-in the desired characteristics.
15-bit fractional-N feedback divider with 4 bits of precise control.
Available with multi-phase outputs.

TSMC 3nm IP