Pcie controller IP

Internal data path size automatically scales up or down (64-, 256-, 512- bits) based on link max. speed and width for reduced gate count and optimal throughput
Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs up to Gen4 x8/Gen3 x16 with same RTL code – Gen5 support pending
Stringent implementation of PCIe to AXI Ordering Rules and AXI to PCIe Ordering Rules guarantees AXI deadlock prevention
Carefully engineered AXI bridge & AXI interconnect allows full performance on AXI interfaces

Internal data path size automatically scales up or down (256-, 512- bits) based on max. link speed and width for reduced gate count and optimal throughput
Dynamically adjustable application layer frequency down to 8Mhz for increased power savings
Optional MSI/MSI-X register remapping to memory for reduced gate count when SR-IOV is implemented
Configurable pipelining enables full speed operation on Intel and Xilinx FPGA, full support for production FPGA designs (when supported)
Ultra-low Transmit and Receive latency (excl. PHY)

Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
Production-proven datapath support for 32b, 64b, 128b, 256b and 512b implementations
Fully compliant with the PCI-SIG Single-Root I/O Virtualization (SRIOV) specification
Application interfaces include the Synopsys native interface or the optional ARM® AMBA® 4 AXI and 3 AXI application interface (AMBA not available for Switch configurations)

Supports all required features of the PCI Express 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
Production-proven datapath support for 32b, 64b, 128b, 256b and 512b implementations
Fully compliant with the PCI-SIG Single-Root I/O Virtualization (SRIOV) specification
Application interfaces include the Synopsys native interface or the optional ARM® AMBA® 4 AXI and 3 AXI application interface (AMBA not available for Switch configurations)

Innosilicon’s PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and PIPE specifications
These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, data centers, cloud servers, AI and machine learning, storage expansion, and high-speed interconnect applications

Implements PCIe 6.0 Specification at 64 GT/s
Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
Designed for easy integration with Alphawave PipeCORE™ PCIe PHY IP
Key IP features configurable to optimize IP for exact application requirements