IP Catalog > PCIe 5.0

PCIe 5.0 IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Search (278)
Compare 278 IP from 22 vendors (1 - 10)
  • PCIe 5.0 Controller with AMBA AXI interface
    • Compliant with the PCI Express 5.0 rev. 0.7 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8-, 16-, 32- and 64-bit) specifications
    Block Diagram -- PCIe 5.0 Controller with AMBA AXI interface
  • PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
    • Complies with the PCI Express Base 4.0 Specification, Rev 4.0
    • Supports Endpoint, Root-Port, Dual-mode, Switch
    • Supports link rate of 2.5, 5.0, 8.0 and 16.0 Gbps per lane.
    Block Diagram -- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
  • PCIe 5.0 Customizable Embedded Multi-port Switch
    • 1 Upstream port
    • Multiple Downstream ports (2 up to 32)
    • x1, x2, x4, x8 PCI Express Core
    Block Diagram -- PCIe 5.0 Customizable Embedded Multi-port Switch
  • PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
    • Fully compliant with PCI Express Base 5.0 electrical specifications
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
    Block Diagram -- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
  • PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation
  • PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC N6 x4, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, TSMC N6 x2, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, TSMC N6 x2, North/South (vertical) poly orientation
  • PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation
    • Supports all required features of the PCIe® 5.0, 4.0, 3.1, 2.1, 1.1, PIPE, and CXL 1.0, 1.1, and 2.0 specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE) supporting more than 36dB channel loss
    • Adaptive receiver equalizer with programmable settings
    Block Diagram -- PCIe 5.0 PHY, NCS,TSMC N6 x4, North/South (vertical) poly orientation
×
Semiconductor IP