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PCI Express 4.0 IP

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Compare 376 IP from 13 vendors (1 - 10)
  • PCI Express 4.0 PHY
    • Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 Specifications
    • Supports all power saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 spec.
    Block Diagram -- PCI Express 4.0 PHY
  • PCI Express Gen 4 PHY
    • Support 16GT 8GT 5GT 2.5GT data rate
    • Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
    • x1, x2, x4, x8, x16 lane configuration with bifurcation
    • Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
  • PCIe 5.0 Controller with AMBA AXI interface
    • Compliant with the PCI Express 5.0 rev. 0.7 (32 GT/s), 4.0 (16 GT/s), 3.1/3.0 (8 GT/s) and PIPE (8-, 16-, 32- and 64-bit) specifications
    Block Diagram -- PCIe 5.0 Controller with AMBA AXI interface
  • PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
    • Complies with the PCI Express Base 4.0 Specification, Rev 4.0
    • Supports Endpoint, Root-Port, Dual-mode, Switch
    • Supports link rate of 2.5, 5.0, 8.0 and 16.0 Gbps per lane.
    Block Diagram -- PCIe 5.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
  • CCIX 32G Premium Controller with AMBA bridge II
    • Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
    • Supports all required features of the PCIe 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
    • Choice of datapath widths (128-bit, 256-bit, or 512-bit)
    • Supports cache-coherency as defined by the CCIX standard
    Block Diagram -- CCIX 32G Premium Controller with AMBA bridge II
  • CCIX 32G Premium Controller II
    • Supports all required features of the CCIX 1.1 specification, including 32GT/s, and ESM support for 25GT/s and 20GT/s
    • Supports all required features of the PCIe 4.0 (16 GT/s), 3.1 (8 GT/s), 2.1 (5 GT/s), 1.1 (2.5 GT/s) and PIPE (8-, 16- and 32-bit) specifications
    • Choice of datapath widths (128-bit, 256-bit, or 512-bit)
    • Supports cache-coherency as defined by the CCIX standard
    Block Diagram -- CCIX 32G Premium Controller II
  • PCI Express - Configurable PCI Express 4.0 IP
    • Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
    • Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
    Block Diagram -- PCI Express - Configurable PCI Express 4.0 IP
  • PCI Express (PCIe) 4.0 Controller
    • Compliant with PCIe 4.0, 3.1, 2.1, and 1.1 specifications
    • 32/16b interface for 500MHz or 1GHz core operation
    • Modes supported: Root Complex, EndPoint, or Dual Mode
    • SR-IOV and multifurcation options
  • CCIX 1.1 Controller
    • Track record of silicon proven PCIe 4.0 designs guarantees first-time silicon success
    Block Diagram -- CCIX 1.1 Controller
  • 25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC N6 x2 North/South (vertical) poly orientation
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