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DPA Countermeasure IP

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Compare 30 IP from 7 vendors (1 - 10)
  • Programmable Root of Trust With DPA and FIA for US Defense
    • Custom-designed 32-bit secure RISC-V processor
    • Multi-layered security model protects all core components against a wide range of attacks
    • Security model includes hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
    • State-of-the-art DPA resistance, FIA protection and anti-tamper techniques
    Block Diagram -- Programmable Root of Trust With DPA and FIA for US Defense
  • Programmable Root of Trust Family With DPA & Quantum Safe Cryptography
    • Hardware Root of Trust employing a custom 32-bit RISC-V processor
    • Multi-layered security model provides protection of all components in the core
    • NIST CAVP and CMVP compliant for FIPS 140-3 validation
    • State-of-the-art anti tamper techniques
    • DPA-resistant cryptographic accelerators
    • Caliptra Root of Trust for Measurement with DICE and X.509 support
    Block Diagram -- Programmable Root of Trust Family With DPA & Quantum Safe Cryptography
  • Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
    • One input word per clock without any backpressure
    • Design can switch stream, algorithm, mode, key and/or direction every clock cycle
    • GCM: throughput is solely determined by the data width, data alignment and clock frequency
    • XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
    Block Diagram -- Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
  • ChaCha20 DPA Resistant Crypto Accelerator
    • Quicken time-to-market using precertified DPA Countermeasures
    • Highly secure cryptographic engine primitives
    • Extensive validation using the Test Vector Leakage Assessment (TVLA) methodology (revealing no leakage beyond 100 million traces)
    • Cores protected against univariate first- and second-order side-channel attacks beyond 1 billion operations
    Block Diagram -- ChaCha20 DPA Resistant Crypto Accelerator
  • AES Authenticated Encryption Accelerator with DPA or with DPA and FIA
    • The SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher acceleration.
    • The cores are easily integrated into ASIC/SoC and FPGA devices and offer a high-level of resistance to various Side Channel Attacks like Differential Power Analysis (DPA), and optionally offer detection of Fault Injection Attacks (FIA).
  • High-speed Inline Cipher Engine
    • The ICE-IP-338 data path can be scaled to widths that are multiples of 128 bit to allow a tradeoff between area and performance that best fits the target application.
    • Configuration options include or exclude support for CipherText Stealing (CTS), the GCM mode, and the SM4 algorithm and/or Datapath Integrity logic.
    • The cryptographic AES and SM4 primitives can be provided with or without side channel attack DPA countermeasures.
    Block Diagram -- High-speed Inline Cipher Engine
  • Inline memory encryption engine, for FPGA
    • Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
    • Supports AES key sizes 128 or 256
    • Internal key management with NIST-compliant key generation
    • Encrypt memory space into user-defined vaults, each with a unique key
    • Compatible with AMBA AXI4 interface
    • Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
    • Supports multiprocessor systems
    Block Diagram -- Inline memory encryption engine, for FPGA
  • Inline memory encryption engine for ASIC SoCs
    • 128/512-bit (16-byte) encryption and decryption per clock cycle throughput
    • Bidirectional design including separate crypto channels for read and write requests, ensuring non-blocking Read
    • Read-modify-write supporting narrow burst access.
    • Zeroization and support for memory initialization
    • Latency: <28 clock cycles for unloaded READ
    Block Diagram -- Inline memory encryption engine for ASIC SoCs
  • Multipurpose Security Protocol Accelerator
    • Highly configurable security accelerator
    • Support for all ciphers, hashes and MAC algorithms used in major protocols such as IPsec, SSL/TLS/DTLS, Wi-Fi, 3GPP LTE/LTE-A, SRTP, MACsec
    • Cipher algorithms: AES, DES/3DES, ChaCha20, MULTI2, KASUMI, SNOW 3G, ZUC
    • Cipher modes: ECB, CBC, CTR, OFB, CFB, f8, XTS, UEA1, UEA2, 128-EEA1, 128-EEA2, 128-EEA3
  • Security Protocol Accelerator for SM3 and SM4 Ciphers
    • Highly customer configurable, silicon-proven security accelerator
    • Support for Chinese security SM3 and SM4 (modes: ECB, CTR, CBC, CCM, GCM, XTS) algorithms
    • Option: Differential Power Analysis (DPA) countermeasures for SM4
    • Built-in scatter/gather DMA capability offloads the host processor
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