Arm Cortex-A72 IP

• Triple-Issue Out-of-Order Pipeline - Dispatch and computational bandwidth improvements over Cortex-A57 have maximize the effectiveness of the triple-issue out-of-order pipeline to remove code dependencies for achieving high peak and sustained instruction throughputs at frequencies above 3GHz in 16FF+ process technology.
• Advanced Branch Predictor - A sophisticated new algorithm drastically improves prediction accuracy which reduces wasted energy consumption from executing down a wrong code path.
• Microarchitecture Efficiency - Every aspect of the Cortex-A57 microarchitecture was optimized to usher in a new level of Cortex-A energy efficiency with dramatic improvements in all aspects of PPA metrics (performance, power, and area).
• Infrastructure Features - Support for networking and storage application with full ECC cache and 44-bit addressing up to 16TB.

Broad market use
Ground-breaking performance
Market-leading efficiency
Brand new memory sub-system