5nm HBM3 IP

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Compare 12 IP from 4 vendors (1 - 10)

TSMC CLN5FF HBM PHY IP
- High Bandwidth Memory (HBM) DRAM PHY
- Supports HBM 3.6Gbps
- Supports DFI 1:2
- Supports only BL4
Up to 50% main memory bandwidth acceleration
- Bandwidth acceleration: 25-50%
- Performance acceleration: 10-25%
- Compression ratio: 2-3x across diverse data sets
High performance and low latency hardware accelerated zram/zswap at unmatched power efficiency
- Compression ratio: 2-4x across diverse data sets
- Compression throughput: 8GB/s
- Decompression throughput: 10.5GB/s
1.2V GPIO
- ESD Protection
- Latch-up Immunity:
TSMC 5nm (N5) 1.2V/1.8V Basekit Libraries
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 5nm (N5) 1.2V/1.8V/2.5V Failsafe GPIO Libraries
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries, multiple metalstacks
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature
TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries
- Supports 1.8V/2.5V/3.3V mixed-voltage-tolerant/failsafe output buffer
- Fully programmable output driver strengths, input Schmitt trigger, and output slew rate
- Supports circuit-under-pad (CUP), non-CUP-inline and staggered-bond pad placement
- Supports retention and bus-keeper feature