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12nm PLL IP

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Compare 123 IP from 10 vendors (1 - 10)
  • TSMC CLN12FFC+ 12nm Ultra PLL - 15MHz-3000MHz
    • New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.
    • Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.
    • Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.
    • Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.
  • TSMC CLN12FFC+ 12nm IoT PLL - 30MHz-1000MHz
    • Optimized for very low power, running completely from core power supply.
    • Supports 32KHz reference clocks.
    • Extremely wide range of operation with multiplication factors over 8,000.
    • Small area, delivered as a single hard macro with guardrings and isolation.
  • TSMC CLN12FFC+ 12nm Deskew PLL - 200MHz-1000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • TSMC CLN12FFC+ 12nm Deskew PLL - 400MHz-2000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • TSMC CLN12FFC+ 12nm Deskew PLL - 800MHz-4000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • GF L12LP 12nm Ultra PLL - 15MHz-3000MHz
    • New state-of-the-art architecture using high-speed digital and analog circuits that offers unprecedented operating ranges and extremely high performance.
    • Ultra low jitter performance for the most demanding SerDes and ADC reference clocks.
    • Ultra wide frequency range with multiplication factors over 250,000 to support 32KHz to 1GHz references.
    • Precise frequency control with a least 26 fractional bits (at least 10 precise) for extremely high fractional-N resolution.
  • GF L12LP 12nm IoT PLL - 30MHz-1000MHz
    • Optimized for very low power, running completely from core power supply.
    • Supports 32KHz reference clocks.
    • Extremely wide range of operation with multiplication factors over 8,000.
    • Small area, delivered as a single hard macro with guardrings and isolation.
  • GF L12LP 12nm Deskew PLL - 200MHz-1000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • GF L12LP 12nm Deskew PLL - 400MHz-2000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
  • GF L12LP 12nm Deskew PLL - 800MHz-4000MHz
    • Designed to eliminate clock distribution latency in systems and individual chips.
    • Precisely aligns the clock distribution output with a reference clock.
    • Provides a zero-delay feedback divider and zero-skew divided clock outputs.
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