USB 3.0 Device IP Core

Overview

A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface.

The USB 3.0 Device IP Core is fully USB 3.0 compliant.

An USB 3.0 Device IP Core is ideal for applications where the target device must act as a peripheral. It provides portable devices with a cost-effective way of conducting high speed point-to-point transfers using the USB bus.

ARCHITECTURE

The USB 3.0 Device IP Core, implements all required functions to transport USB 3.0 traffic.

This includes the PHY Layer, which implements support functions required to talk to a USB 3.0 PIPE complaint PHY interface; The Link and Protocol layers that implement the USB 3.0 link management, transaction management and data transfers; and the Transport Layer, which provides and interface to external interfaces.

 

Key Features

  • USB 3.0 SuperSpeed support, 5Gbit/s
  • USB 3.0 PIPE interface (and V5/V6 GTX)
  • Integrated DMA engine
  • Up to 16 fully configurable endpoints
  • Bulk, control, interrupt and isochronous  endpoints and transfers 
  • Automatic Link Control and Management  performed in hardware
  • User transparent error
  • User transparent error recovery and retransmission of packets
  • Automatic Power State transition performed  in hardware (all power states supported)
  • Autonomous operation with very little firmware interaction
  • Full duplex operation support
  • System Interface:
    • AHB 
    • AVALON
    • OCP 
    • PLB
    • OPB
    • WISHBONE
    • Customer specified bus interface
  •  Compact and cost-effective solution

Benefits

  • High Performance
  • Low Cost
  • Easy to integrate

Block Diagram

USB 3.0 Device IP Core Block Diagram

Applications

  • Consumer
  • Industrial

Deliverables

  • Verilog or Netlist
  • Test bench
  • Documentation
  • Tech Support
  • Reference Design

Technical Specifications

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Semiconductor IP