UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
Overview
UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.
Technical Specifications
Foundry, Node
UMC 55nm
Maturity
Silicon proven, Formal release
UMC
Pre-Silicon:
55nm
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