Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HPC process
Overview
UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track ECO_M1 Cell Library (C35).
Technical Specifications
Foundry, Node
UMC 28nm HPC
UMC
Pre-Silicon:
28nm
HLP
,
28nm
HPM
,
28nm
LP
Related IPs
- Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
- Standard Cell (ECO) Library IP, RVT, 7 tracks, UMC 28nm HLP process
- CMM lane operating from 1.25G~8G ,UMC 28nm HPC Process
- Analog part of TX+RX lane operating at 1.25G~8Gbps , UMC 28nm HPC Process
- Standard Cell (MiniLib) Library IP, RVT, 7 tracks, UMC 55nm SP process
- Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process