SPI Slave IIP

SPI Slave interface provides full support for the both three and four wire SPI synchronous serial interface, compatible with SPI specification SPI Block Guide V04.01. Through its SPI compatibility, it provides a simple interface to a wide range of low-cost devices. SPI Slave IIP is proven in ASIC.The host interface of the SPI can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SPI Slave IIP is supported natively in Verilog and VHDL

• Compliant with SPI Block Guide 4.01 Specification.
• Full SPI Slave functionality.
• Supports flexible transfer format to work with slower interfaces
• Supports Single, Dual, Quad, Octal data widths
• Supports clock less operations.
• Suitable for lower power operations.
• Simple command/Address/data format for SPI slave devices.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices
• Optionally this core can be built to have I2C interface for application where slave can have multiple interfaces like SPI or I2C Interface.

• Single Site license option is provided to companies designing in a single site.
• Multi Sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The SPI Slave interface is available in Source and netlist products.
• The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and linux driver package
• Documentation contains User's Guide and Release notes.