Single Lane and Quad Lane 5Gbps PCIe2.0 PHY IP in TSMC 28HPC process

Overview

TERMINUS CIRCUITS PCIe GEN2.0 PHY is high performance, low power, low latency Single & Quad-Lane PCI Express PHY that supports PCI Express protocol and its signalling needs. It has features like clocking and clock & Data recovering, Serialization and De-Serialization of Data, 8/10b, data coding, Receiver detection.

TERMINUS CIRCUITS’s PCIe GEN 2.0 PHY uses 32/16bit Data PIPE interface. It also supports lower power management states like L0s, L1, L1-sub-states and L2. PCIe Gen 2.0 PHY IP is available in TSMC 28nm HPC process.

* A limited number of Test Chips manufactured in TSMC 28HPC (Single lane and Quad Lanes) are available for Early customers. Contact us for more details.

Key Features

- Quad PCIe 5/2.5 Gbps per lane
- Tight skew control of less than 1UI between lanes of the PMA
- Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- Lowest latency
- Continuous time linear equalizer (CTLE) with programmable settings
- Programmable/automatic calibration of key circuits
- Support for bifurcation and quadfurcation modes
- Multi-tap Rx DFE (decision feedback equalizer)
- Programmable int./ext. loopback modes between TX and RX
-SRnS (Separate Reference no Spread) suppor
- Includes ESD structures
- Operation across a wide temperature range (-40 C to +125 C)

Benefits

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Applications

Enterprise computing
Storage networks
Automotive
GPU interfacing
Server connectivity
Network-on-Chip (NoC)

Deliverables

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Technical Specifications

Foundry, Node

TSMC 28HPC

Maturity

Silicon Ready (Test Chips available in TSMC 28HPC)

Availability

Now

TSMC

Silicon Proven: 28nm HPC

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