Silterra 0.18um Ultra Low Leakage 7track Std Cell Library
Silterra 0.18um ULL Process 7track Std Cell Library
Overview
Key Features
- Silterra 0.18um Ultra Low Leakage Process
- Wide Variety of Cell Functions and Drive Strengths.
- Process-Specific Optimization for Ultra High-Density and Low-Power.
- Engineered for Synthesizability and Routability.
- Scan Flip-flops for Design for Testability Support.
- Clock Gating for power optimization
- More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp
Technical Specifications
Maturity
Pre-Silicon
Related IPs
- HHGrace 0.18um ULL Process 7track Std Cell Library
- Silterra 0.18um ULL Process Multiple power supply IO library with high voltage tolerance
- HHGrace 0.11um ULL Process 6track Std Cell Library
- Silterra 0.18um ULL Process 7track Power Management Kit
- HHGrace 0.11um ULL MVT 7track Std Cell Library
- HHGrace 0.11um ULL 7track Std Cell Library