IP Catalog > Interface IP > Memory Interface IP > DDR IP > DDR4 IP > DDR4 PHY IP > SDRAM DDR4/3/2 & LPDDR4/3/2 Hardened PHY - TSMC 28nm

SDRAM DDR4/3/2 & LPDDR4/3/2 Hardened PHY - TSMC 28nm

Overview

Dolphin s hardened DDR4/3/2 SDRAM PHY and LPDDR4/3/2 SDRAM PHY IP is a silicon-proven, Combo PHY supporting speeds up to 3200 Mbps. It is fully compliant with the DFI 4.0 specification, and features include slew rate control, per-bit de-skew, gate training, read and write leveling and built-in self test (BIST).

In addition, our PHY IP is optimized to provide a complete solution when combined with Dolphin s DDRx and LPDDRx SDRAM Memory Controller IP.

Key Features

  • + DDR4/DDR3/DDR2 PHY IP fully compliant with the DFI 4.0 Specification
  • + LPDDR4/LPDDR3/LPDDR2 PHY IP fully compliant with the DFI 4.0 Specification.
  • + Support speeds up to 3200Mbps with 1.8V oxide and 1600Mbps with 2.5V Oxide.
  • + IP is split into 2 hard macros.
  • + One for commands, control and address pins and another for 8-bit data bus.
  • + Can support custom number of address bits.
  • + Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
  • + Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
  • + JTAG signals also provided for Mentor/Synopsys and LogicVision
  • + Built in Self Test with a Pseudo Random Pattern Generator
  • + Built with Scannable flops
  • + Can be used in wirebond, flip-chip and cup configurations

Deliverables

  • + Encrypted Verilog/SystemVerilog RTL, or post-synthesis netlist
  • + Synthesis and STA scripts
  • + User guide documents
  • + SV/UVM Verification suite with BFM

Technical Specifications

Foundry, Node
TSMC 28nm
Maturity
Pre Silicon
Availability
Yes
TSMC
Pre-Silicon: 28nm HP , 28nm HPC , 28nm HPCP , 28nm HPL , 28nm HPM , 28nm LP
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