The QDRII SRAM Controller MegaCore® function provides an easy-to-use interface to QDRII SRAM and QDRII+ SRAM modules. The QDRII SRAM controller ensures that the placement and timing are in line with QDRII specifications. The QDRII SRAM controller’s local interface is compatible with the Altera® Avalon® Memory-Mapped interface, for easy integration into SOPC builder.
The QDRII SRAM Controller MegaCore functions optimized for Altera Stratix® series FPGAs. The advanced features available in these devices allow you to interface directly to QDRII SRAM devices.
The IP Toolbench-generated example design instantiates a phase-locked loop (PLL), an optional delay-locked loop (for Stratix II FPGAs only), an example driver, and your QDRII SRAM Controller custom variation. The example design is a fully-functional example design that can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller and checks the read data to produce the pass/fail and test complete signals. You can replace the QDRII SRAM controller encrypted control logic in the example design with your own custom logic, which allows you to use the Altera clear-text resynchronization and pipeline logic and datapath with your own control logic.
QDRII SRAM Controller
Overview
Key Features
- Support for QDRII and QDRII+ SRAMs
- Support for burst of two and four memory type
- Support for 8-bit, 18-bit, and 36-bit QDRII SRAM interfaces
- Flexible and robust design
- Support for two-times and four-times data width on the local side (four-times for burst of four only)
- Automatic concatenation of consecutive reads and writes (narrow local bus width mode only)
- Intellectual property (IP) functional simulation models for use in VHDL and Verilog HDL simulators supported by Altera
- Easy-to-use IP Toolbench interface and example design
- Support for OpenCore Plus evaluation
Technical Specifications
Maturity
I-Tested
Availability
Now