MIPI I3C PHY I/O

Overview

Arasan’s MIPI I3C(R) PHY I/O IP, in compliance with MIPI I3C(R) specifications v1.1. Arasan’s MIPI I3C(R) PHY IP is part of Arasan’s Total IP Solution for MIPI I3C(R) v1.1. Arasan’s 2-wire MIPI I3C(R) PHY I/O consolidates the features of I2C and SPI leading to an overall low pin count, shorter signal path, simplified design, and reduced power and cost. It operates in sync with the IP core’s clock rates up to 12.5 MHz and also provides options for higher performance and high data rates.

Key Features

  • Compliant with MIPI I3C Specification.

Deliverables

  • RMM compliant synthesizable RTL design in Verilog
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documents
  • Validated with 3rd Party UVM-based Slave VIP and available as an additional option

Technical Specifications

Maturity
Silicon proven
Availability
NOW
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Semiconductor IP