Low Power/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF
Overview
Specialty Memory Solutions
Technical Specifications
Foundry, Node
TSMC 55nm
Maturity
Silicon Proven
TSMC
Silicon Proven:
55nm
FL
,
55nm
G
,
55nm
GP
,
55nm
LP
,
55nm
NF
,
55nm
ULP
,
55nm
ULPEF
,
55nm
UP
Related IPs
- High Performance/Low Power/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process HP/HPC/HPC+/HPL/HPM/LP/ULP
- Low Power/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process G/LP/LP_eDRAM/ULP/ULPEF
- Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process FF+GL/FF+LL/FFC
- Ultra Low Leakage/Ultra Low Power Via Programmable ROM Compiler with Row/Column Redundancy Option, supports process ULL/ULP
- Low Power/Ultra Low Power Dual Port SRAM Compiler with Row/Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF
- Low Power/Ultra Low Power Pseudo 2 Ports SRAM Compiler with Row/Column Redundancy Option, supports process GP/LP/LPEF/ULP/ULPEF