JESD207 Verification IP

Overview

The SmartDV's JESD207 verifies the Radio Front end-Baseband digital parallel interface.JESD207 Verification IP can be used to verify BBIC or RFIC following the JESD207 basic protocol as defined in JESD207 and provides the following features.

JESD207 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

JESD207 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports JESD207 specification.
Operates as BBIC (Baseband IC) and RFIC (Radio front end IC) monitor.
Supports half duplex data transfer.
Supports DDR source synchronous data transfer timing.
Supports both data path transaction and control plane transactions.
Supports multiple parallel sample streams in BBIC and RFIC data path interface.
Supports data path transaction

Supports transmit burst and receive burst
Supports both 10 bits and 12 bits sample width
Supports 2 way interleave and 4 way interleave transactions
Supports 1T1R,1T2R,2T2R systems

Supports control plane transaction

Supports 4 wires write and 4 wires read
Supports 3 wires write and 3 wires read
1bit command plus 7bit address control field format
Serial clock can be stopped between transactions for reducing control plane power consumption to negligible levels
Extended data tranactions

Supports various kinds of errors

Mixed data error
Invalid address error

Status counters for various events on bus.
Supports constraints randomization.
Built in functional coverage analysis.
Callbacks in BBIC and RFIC for various events.
Test suite to test each and every feature of JESD207 specification.

Benefits

Faster test bench development and more complete verification of JESD207 designs.
Simplifies results analysis.
Runs in every major simulation environment.
Easy to use command interface simplifies testbench control and configuration of BBIC and RFIC.
Comes with complete test suite to test each and every feature of JESD207.

Block Diagram

Deliverables

Complete regression suite containing all the JESD207 testcases.
Examples showing how to connect various components,and usage of BBIC,RFIC and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation contains User's Guide and Release notes.

Technical Specifications

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