The synchronous I2C interface is a block that interconnects an APB bus. The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C bus. The APB interface is used to easily integrate the Bridge Controller for any SOC implementation.
The APB - I2C is a host/device interface that enables synchronous serial communication with the other host or device I2C peripherals having I2C compatible interface. The controller performs the following functions:
•Parallel-to-serial conversion on data written to an internal 8bit wide, 1024 deep FIFO.
•serial-to-parallel conversion on received data, buffering it in a similar 8-bit wide, 1024 deep FIFO
Device states are read by the APB using status registers that reflect the completion of I2C transfers.
I2C Host / Device Bus Controller
Overview
Key Features
- I2C Interface
- Compliant with I2C specification Version 2.1
- Supports a simple bi-directional 2-wire bus for efficient for inter-IC control
- Programmable as I2C Host mode
- Programmable as I2C Device mode
- Supports a Clock generation circuitry to derive I2C clock from APB clock
- Supports various operational frequencies from 100 KHZ to 400 KHZ.
- 1024x8 bits register space is memory mapped to external I2C Master.
- APB Interface
- Compliant with AMBA [Rev2.0] for easy integration with SOC implementations
- Supports APB bus for varying frequency range from 1 to 95MHZ.
- Supports Bus mastering DMA modes.
- Device states are read by periodic polling mechanism.
- Has 1024X 8 FIFO to accelerate the data transfers from and to I2C and APB.
- 1024x8 bits register space is mapped to APB memory.
Deliverables
- Verilog HDL
- Synopsys synthesis scripts
- Test Environment and test scripts
- APB - I2C controller’s Userguide with full programming interface and parameterization instructions
Technical Specifications
Maturity
Silicon proven
Availability
NOW