The Synopsys HDMI Receiver (RX) IP solutions are compliant with the High- Definition Multimedia Interface (HDMI) 2.0 and 1.4 specifications and provide the necessary logic to implement and verify designs for various consumer electronic applications.
The power- and area-optimized HDMI RX IP solutions include a suite of configurable digital controllers and high-speed, mixed-signal PHY IP. Shipping in volume and having gone through extensive in-house and third-party interoperability testing, the IP solutions enable system-on-chip (SoC) designers to lower integration risk and accelerate time-to-market.
Synopsys’ complete HDMI IP solution consists of digital controllers, High- Bandwidth Digital Content (HDCP) embedded security modules (ESMs), PHYs and verification IP as well as IP Prototyping Kits with associated software and drivers.
HDMI 2.0 RX 1P PHY 6Gbps in TSMC (28nm)
Overview
Key Features
- Aggregate bandwidth of 18 Gbps to support up to 4K x 2K resolution at 60 Hz frame rate and 8-bit per color for a flickerless ultra high-definition experience
- 1, 2, or 4 input ports
- Four levels of equalization for long cable support and clean signals
- Adaptive equalization in RX core to compensate for the signal attenuation and inter-symbol interference caused by long cables
- Integrated auto-calibrated 50? input termination resistors in RX core
- Hot Plug Detect allows changing of cables and components without switching off the entire system
- Integrated test features including scope, BIST and loopbacks
- Optimized pin count, small area to ensure low BOM cost
- Integrated audio return channel (ARC)
- Support for 5V IO on all nodes (down to 28-nm nodes)
- Aggressive ESD protection
- Input clock from 25 MHz to 600 MHz range
Benefits
- Silicon-proven HDMI RX IP includes digital controllers, HDCP embedded security modules, PHYs, verification IP and IP Prototyping Kits
- HDMI 2.0 and HDCP 2.3 certified
- Support for key HDMI 2.0 features such as 4K x 2K resolution at 60 Hz frame rate, YCbCr 4:2:0 pixel encoding format, TMDS scrambling, CEC 2.0 and 18.0 Gbps aggregate bandwidth
- Optimized for low power and small area
- Integrated audio return channel (ARC) block
- 1-, 2-, or 4-port inputs with fast switching
- Timing hardened blocks simplify placement and design closure
- High-performance RX PHY IP enables long cable lengths
- Configurable controller architecture optimized for power, performance, and area
Applications
- Digital TVs, monitors and projectors
- Audio/video receivers
- Sound bars
- Set-top boxes
Deliverables
- Databook
- Application notes
- Assembly guidelines
- Design files kit: Behavioral model; .LEF file; .LIB file; GDSII layout database
Technical Specifications
Foundry, Node
TSMC 28nm - HPC+, HPC
Maturity
Available on request
Availability
Available
TSMC
Pre-Silicon:
28nm