Vendor: Small World Communications Category: Channel Coding

64/256 state block Viterbi decoder

The VA08S is a low complexity 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm.

Contact Provider Request Datasheet

Overview

The VA08S is a low complexity 64 or 256 state error control decoder using the maximum likelihood Viterbi algorithm. The decoder is designed to efficiently decode short block lengths with maximum flexibility, allowing it to decode various communications standards, as well as custom coding solutions.

Key features

  • 64 or 256 state (constraint length 7 or 9) Viterbi decoder
  • Up to 213 MHz internal clock
  • Rate 1/2, 1/3, or 1/4 (inputs can be punctured for higher rates)
  • 4–bit received signed magnitude data
  • Up to length 64 block decoding including tail
  • Estimated channel bit error outputs
  • 725 slices and 4 BlockRAMs (Virtex, Virtex-E, Spartan-II, Spartan-IIE), 670 slices and 1 BlockRAM (Virtex-II, Virtex-II Pro) or 707 slices and 1 BlockRAM (Spartan-3, Virtex-4)
  • Asynchronous logic free design
  • Available as EDIF core and VHDL simulation core for Xilinx Virtex, Virtex-E, Spartan-II, Spartan-IIE, Virtex-II, Virtex-II Pro, Spartan-3 and Virtex-4 FPGAs under SignOnce IP License. Actel, Altera and Lattice FPGA cores available on request.
  • Available as VHDL core for ASICs
  • Low cost university license also available
  • 64 State Features
    • Up to 17.6 Mbit/s decoding speed
    • Optional or standard code polynomials
  • 256 State Features
    • Up to 5.3 Mbit/s decoding speed
    • Optional or 3GPP/3GPP2 code polynomials

What’s Included?

  • EDIF Core
  • VHDL Simulation Core
  • Test Vector Generation Software

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Specifications

Identity

Part Number
VA08S
Vendor
Small World Communications
Type
Silicon IP

Provider

Small World Communications
HQ: Australia
Small World Communications was started in January 1997 and is located in Adelaide, Australia. We specialise in error control decoder products for programmable gate arrays.
Contact Small World Communications

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

Audio Transport in DisplayPort VIP

DisplayPort uses Secondary Data Packets (SDPs), which are transported over the Main-Link that are not main video stream data. This allows it to carry audio and video simultaneously. The VIP supports audio transmission both in the original mode as defined in the specification as well as just as any other SDP being transmitted.

Frequently asked questions about Channel Coding IP cores

What is 64/256 state block Viterbi decoder?

64/256 state block Viterbi decoder is a Channel Coding IP core from Small World Communications listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP