6 track High Density standard cell library at TSMC 55 nm
Overview
Foundry Sponsored, TSMC 55 uLP, SESAME HD DV provides the best trade-off between area and power achieved from an innovative cell design enabling 6-track cells and 1P3M SoC implementation.
Key Features
- High Density optimization
- 6-Track high cells for optimal area reduction
- Only Metal 1 used for cell design
- Compatible with 1P3M SoC implementation
- with island construction kit
Technical Specifications
Maturity
Pre-silicon
TSMC
Pre-Silicon:
55nm
ULP
Related IPs
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- 6 track High Density standard cell library at TSMC 180nm
- 6 track Ultra High Density standard cell library at TSMC 55 nm