3.3V General Purpose I/O Inline Pad Set

Overview

The 3.3V GPIO library provides general purpose bidirectional I/O cells. These programmable, multi-voltage I/O’s give the system designer the flexibility to design to a wide range of performance targets.

These 22nm libraries are available in inline and staggered CUP wire bond implementations with a flip chip option.

To design a functional I/O power domain with these cells, an additional library is required – 3.3V Support: Power. That library contains an input-only buffer, isolated analog I/O, and a full complement of power cells along with corner and spacer cells to assemble a complete pad ring by abutment. An included rail splitter allows multiple power domains to be isolated in the same pad ring while maintaining continuous VDD/VSS for robust ESD protection.

Key Features

  • Bidirectional GPIO Driver Features
  • ? Multi-Voltage (1.2V, 1.5V, 1.8V, 2.5V, 3.3V)
  • ? LVCMOS / LVTTL input with selectable hysteresis
  • ? Programmable drive strength (rated 2mA to 12mA)
  • ? Selectable output slew rate
  • ? Optimized for EMC with SSO factor of 8
  • ? Open-drain output mode
  • ? Programmable input options (pull-up/pull-down/repeater)
  • ? Power-On Start (POS) capable
  • ? Power sequencing independent design with Power-On Control

Deliverables

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Technical Specifications

Foundry, Node
GLOBALFOUNDRIES, 22nm
Maturity
Silicon Proven
Availability
Available Now
GLOBALFOUNDRIES
Pre-Silicon: 22nm FDX
×
Semiconductor IP