multi-die interLink IP
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SLM Signal Integrity Monitor
- The SLM Signal Integrity Monitor (SIM) IP enables signal quality measurement for die-to-die interfaces. It can be implemented in silicon with minimal area overhead. It enables accurate measurement of silicon interconnects with real-time reporting for analytics.
- With the use of Monitor, Test and Repair (MTR), this real-time reporting enables structural lane monitoring, aging related degradation, and optional repair of failing lanes to maintain high-speed performance throughout the silicon lifecycle.
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UCIe Controller add-on CXL2 Protocol Layer
- UCIe Controller add-on CXL2 Protocol Layer
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UCIe Controller add-on CXL3 Protocol Layer
- UCIe Controller add-on CXL3 Protocol Layer
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UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
- Low latency controller for UCIe-based multi-die designs
- Includes Die-to-Die Adapter layer and Protocol layer
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Universal Chiplet Interconnect Express (UCIe™) PHY
- Supports up to 32Gbps per pin including 4/8/12/16/24Gbps
- Forwarded clock, track, and valid pins
- Sideband messaging for link training and parameter exchange
- KGD (Known Good Die) testing capability
- Redundant lane repair (advanced)
- Width degradation (standard)
- Lane reversal
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112G PHY, TSMC N7 x4, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
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112G Ethernet PHY, TSMC N7 x4, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
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112G Ethernet PHY, TSMC N7 x2, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
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112G Ethernet PHY, TSMC N7 x1, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
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112G Ethernet PHY, TSMC N6 x2, North/South (vertical) poly orientation
- Supports full-duplex 1.25 to 112Gbps data rates in several lane configurations
- Enables 100G, 200G, 400G, 800G Ethernet interconnects for wired and optical network infrastructure
- Supports IEEE 802.3ck and OIF standards electrical specifications
- Meets the performance requirements of multi-die, co-packaged optics, near-packaged optics, chip-to-chip, chip-to-module, and backplane interconnects
