memory controller with execute in place IP
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SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
- Set of software accessible control registers to execute any Flash memory command
- Supports any device clock frequency, polarity and phase,
- Programmable baud rate generator,
- Built in FLASH Commands decoder supports most popular FLASH devices,
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FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
- Set of software accessible control registers to
- execute any Flash memory command
- Support for most popular SPI like FLASH memories and PSRAM
- Supports any device clock frequency, polarity and phase
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QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
- Set of software accessible control registers to execute any Flash memory command
- Supports any device clock frequency, polarity and phase,
- Programmable baud rate generator,
- Built in FLASH Commands decoder supports most popular FLASH devices,
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AHB Performance Subsystem - ARM M0
- Supports Cortex-M0 (or equivalent) processor
- AMBA® 2.0 (AHB)
- AHB Multi-matrix bus infrastructure
- External Nor Flash controller
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AHB Performance Subsystem - ARM M3
- Supports Cortex-M3/M4 (or equivalent) processor
- Power Management Unit
- AMBA® 2.0 (AHB)
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AXI Performance Subsystem
- Supports Cortex-A5 (or equivalent) processor
- AMBA® 4.0 (AXI)
- AXI Multi-layer bus infrastructure
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AHB Subsystem
- Subsystem for microprocessors with 32-bit AMBA® 3.0 AHB-Lite or AHB Interfaces, such as: BA2x, ARM Cortex-M0/M1M3/M4, and Several RISC-V processors
- AHB-SBS-BASE integrates: AHB Multi-Layer Interconnect, xSPI Controller, SRAM Controller, and APB Subsystem (APB-SBS) (I2C, SPI, UART. GPIO, RTC. Timer, WDT, and PIC)
- AHB-SBS-EXT adds: Multichannel DMA, SPI-to-AHB bridge, and External parallel flash or SRAM controller
- Highly configurable and customizable
