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memory controller with execute in place IP

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  • SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
    • Set of software accessible control registers to execute any Flash memory command
    • Supports any device clock frequency, polarity and phase,
    • Programmable baud rate generator,
    • Built in FLASH Commands decoder supports most popular FLASH devices,
  • AXI Quad SPI Controller with Execute in Place (XIP)
    • The Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache architecture.
    • This architecture enhances system performance, scalability, power efficiency, data locality, application responsiveness, cost optimization, and market competitiveness, providing a distinctive business value.
    Block Diagram -- AXI Quad SPI Controller with Execute in Place (XIP)
  • AHB Octal SPI Controller with PSRAM and XIP Support
    • The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
    • In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus.
    Block Diagram -- AHB Octal SPI Controller with PSRAM and XIP Support
  • FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
    • Set of software accessible control registers to
    • execute any Flash memory command
    • Support for most popular SPI like FLASH memories and PSRAM
    • Supports any device clock frequency, polarity and phase
  • QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
    • Set of software accessible control registers to execute any Flash memory command
    • Supports any device clock frequency, polarity and phase,
    • Programmable baud rate generator,
    • Built in FLASH Commands decoder supports most popular FLASH devices,
    Block Diagram -- QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
  • XSPI Controller IIP
    • Compliant with XSPI protocol of JEDEC standard version 1.0 specification
    • Support single master and multiple slaves per interface port
    • Support source synchronous clocking
    • Support Deep power down enter and exit commands
    Block Diagram -- XSPI Controller IIP
  • AHB Performance Subsystem - ARM Cortex M0
    • The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional performance.
    • This AHB Multi-matrix system contains a flexible Power Management Unit for controlling power sequencing of the CPU and peripherals.
    • The PMU can easily be extended to control additional cores, peripherals and even analog subsystems on the same SOC

     

    Block Diagram -- AHB Performance Subsystem - ARM Cortex M0
  • AHB Performance Subsystem - ARM Cortex M3
    • The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional performance.
    • This AHB Multi-matrix system contains a flexible Power Management Unit for controlling power sequencing of the CPU and peripherals.
    • The PMU can easily be extended to control additional cores, peripherals and even analog subsystems on the same SOC.
    Block Diagram -- AHB Performance Subsystem - ARM Cortex M3
  • AXI Performance Subsystem - ARM Cortex A
    • The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance.
    • This system contains an 8 Master component, 16 Slave component AXI4 multi-matrix for supporting multiple high speed user AXI Master components while providing high performance with Cortex-A5 class processors.
    Block Diagram -- AXI Performance Subsystem - ARM Cortex A
  • AHB Subsystem
    • The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus interfaces such as the BA22-DE, BA22-CE, ARM Cortex-M0/M0+/M1/M3/M4, and several RISC-V processors.
    • The AHB subsystem is available in two versions
    Block Diagram -- AHB Subsystem
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