automotive RISC-V processor IP
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32-bit RISC-V processor specifically designed for the Automotive and Functional Safety markets
- 32-bit RISC-V ISA
- ASIL B and ASIL D area optimised product variants
- Functional Safety Package and Independent Assessment
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Integrated Secure Element (iSE) for multiple applications
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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Integrated Secure Element (iSE) for automotive
- Services:
- Secure Boot
- Secure Firmware update
- Life-cycle management
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RT-640 Embedded Hardware Security Module (HSM) for Automotive ASIL-B
- Custom-designed 32-bit RISC-V secure processor
- Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
- Multi-layered security model protects all core components against a wide range of attacks
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IP Platform for BLE 5.2 IoT Sensors
- LE 5.2 CONTROLLER :
- NEURAL NETWORK PROCESSOR :
- SECURITY ACCELERATOR :
- AMBA standard interface : AXI/AHB/APB
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AI-Enabled RISC-V Automotive CPU for ADAS and Autonomous Vehicles
- High-performance 64-bit RISC-V application processor
- 2-way simultaneous multi-threading
- ASIL-B capable safety element out context
- Tightly-coupled accelerator interfaces
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Highly scalable inference NPU IP for next-gen AI applications
- Matrix Multiplication: 4096 MACs/cycles (int 8), 1024 MACs/cycles (int 16)
- Vector processor: RISC-V with RVV 1.0
- Custom instructions for softmax and local storage access
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4x improvement to vector computation with 4x sustained bandwidth of prior generations
- 1024-bit VLEN
- SiFive Intelligence Extensions for ML workloads
- 512-bit vector register length processor
- Performance benchmarks
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Highest performance Six-wide, out-of-order core with a shared cluster cache enabling up to a 32-core cluster
- Full support for the RVA22 RISC-V profile specification and Vector 1.0 and Vector Crypto for enabling 64-bit apps processors running feature rich OS stacks such as Linux and Android.
- Breakthrough RISC-V performance
- >12 SpecINT2k6/GHz (P870 Processor)
- P800-Series Architectural Features
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RT-645 Embedded Hardware Security Module (HSM) for Automotive ASIL-D
- Custom-designed 32-bit RISC-V secure processor
- Security model include hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator, AXI Multi Issue Out-of-Order, and Fast DMA capability. Additional algorithms such as Whirlpool (SHE), SHA-1 (legacy), AES-CMAC, SHA-3, Poly1305, ChaCha and OSCCA SM2-3-4 are available
- Multi-layered security model protects all core componentsagainst a wide range of attacks
