USB Audio Device Class 3.0 IP
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13
IP
from 4 vendors
(1
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10)
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24bit Audio CODEC in 130nm~14nm
- ? DAC SNR 93dB (‘A’ weighted), THD –87dB at 48kHz, 2.5V
- ? ADC SNR 91dB (‘A’ weighted), THD -81dB at 48kHz, 2.5V
- ? Programmable ALC / Noise Gate
- ? 2x On-chip Headphone Drivers
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Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
- Fully compliant with USB PD Specification revision 3.0 and Type-C Cable and Connector specification revision 1.2
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USB 2.0 picoPHY in GF (40nm, 28nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Small PHY macro area
- Low power
- Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
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USB 2.0 femtoPHY in GF (28nm, 22nm, 12nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
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USB 2.0 femtoPHY in GF (22nm) for Automotive Grade 1
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
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USB 2.0 femtoPHY in TSMC (16nm, N7) for Automotive
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors
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USB 2.0 picoPHY in UMC (40nm, 28nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Small PHY macro area
- Low power
- Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
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USB 2.0 picoPHY in TSMC (40nm, 28nm)
- Complete mixed-signal physical layer for single-chip USB 2.0 OTG and non-OTG applications
- Small PHY macro area
- Low power
- Advanced power management features, including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
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USB 2.0 femtoPHY in Samsung (14nm, 11nm, 8nm, 7nm, 5nm, SF4X)
- Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
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USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
- Complete mixed-signal physical layer for single-chip USB 2.0 Host, Device, and Dual Role applications Small PHY macro area: as small as 0.20 mm2
- Low power: as low as 50mW (during high-speed packet transmission)
- Advanced power management features including support for power supply gating, supply scaling, ultra-low standby current support, and power management unit (PMU) interrupt support
- Supports USB 2.0 ID-pin detection and OTG Voltage Detectors