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Secured 1553 IP

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Compare 35 IP from 10 vendors (1 - 10)
  • AXI Interconnect
    • The AXI MATRIX-IP component is a multi-layer interconnect implementation of the AXI protocol, which is designed for high-performance, high-frequency system designs.
    • AXI MATRIX-IP is highly configurable with the capacity to handle up to 16 Masters and Slaves. IP can be configured to support AXI3, AXI4-Lite or AXI4
    Block Diagram -- AXI Interconnect
  • Crystal-less Low Power Oscillator on TSMC CLN28HPC+
    • Crystal-less oscillator
    • Uses standard CMOS transistors
    • Accuracy within +/-35% untrimmed, +/-8% post-trim
    • Under 50uA active power
  • Crystal-less Low Power Oscillator on TSMC CLN16FFC
    • Crystal-less oscillator
    • Uses standard CMOS transistors
    • Accuracy within +/-35% untrimmed, +/-8% post-trim
    • Under 50uA active power
  • Crystal-less Low Power Oscillator on TSMC CLN12FFC
    • Crystal-less oscillator
    • Uses standard CMOS transistors
    • Accuracy within +/-35% untrimmed, +/-8% post-trim
    • Under 50uA active power
    Block Diagram -- Crystal-less Low Power Oscillator on TSMC CLN12FFC
  • Automotive Grade 1 – Crystal-less Oscillator on GLOBALFOUNDRIES 22FDX-AG1
    • Crystal-less oscillator
    • Uses standard CMOS transistors
    • Under 50uA active power
    • Quick start/stop capability
  • 100MHz Crystal-less Oscillator on TSMC CLN6FF
    • Crystal-less oscillator
    • Uses standard CMOS transistors
    • Under 75uW active power
    • Quick start/stop capability
  • GDDR7 Synthesizable Transactor
    • Supports GDDR7 memory devices from all leading vendors.
    • Supports 100% of GDDR7 protocol draft JEDEC specification.
    • Supports all the GDDR7 commands as per the specs.
    • Supports 4 separate independent channels with point-to-point interface for data, address and command.
    Block Diagram -- GDDR7 Synthesizable Transactor
  • GDDR6 Synthesizable Transactor
    • Supports 100% of GDDR6 protocol standard JESD250, JESD250A, JESD250B and JESD250C specification with version 3.12
    • Supports all the GDDR6 commands as per the specs
    • Supports 2 separate independent channels with point-to-point interface for data, address and command
    • Supports double data rate (DDR) or quad data rate (QDR) data
    Block Diagram -- GDDR6 Synthesizable Transactor
  • Wide Range VCC Flash Memory Model
    • Supports Wide Range VCC Flash memory devices like MX25R3235F, MX25R1635F, MX25R6435 from all leading vendors
    • Supports 100% of Wide Range VCC Flash protocol standards.
    • Supports all the Wide Range VCC Flash commands as per the specs.
    • Supports Serial Peripheral Interface - Mode 0 and Mode 3
    Block Diagram -- Wide Range VCC Flash Memory Model
  • GDDR7 Memory Model
    • Supports GDDR7 memory devices from all leading vendors.
    • Supports 100% of GDDR7 protocol draft JEDEC specification.
    • Supports all the GDDR7 commands as per the specs.
    • Supports 4 separate independent channels with point-to-point interface for data, address and command.
    Block Diagram -- GDDR7 Memory Model
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