IP Catalog > Secure Boot Hardware Engine

Secure Boot Hardware Engine IP

Filter
Filter
Search (11)
Compare 11 IP from 5 vendors (1 - 10)
  • Secure Boot Hardware Engine
    • Protection Layers
    • Public-Key Authentication Benefits
    • Fast & Compact
    Block Diagram -- Secure Boot Hardware Engine
  • SHA-3 Crypto IP Core
    • Area efficient
    • High throughput
    • Compliant to NIST’s FIPS 202 standard
    Block Diagram -- SHA-3 Crypto IP Core
  • Root of Trust eSecure module for SoC security
    • Secure Boot
    • Firmware update in the field
    • Secure key storage
    Block Diagram -- Root of Trust eSecure module for SoC security
  • Security Enclave IP based on RISC-V
    • Secure Boot
    • Firmware update in the field
    • Secure key storage
    Block Diagram -- Security Enclave IP based on RISC-V
  • PUF-based Secure Crypto Coprocessor
    • Provide a much easier to adopt hardware RoT with less vulnerability
    Block Diagram -- PUF-based Secure Crypto Coprocessor
  • PUF-based Hardware Root of Trust
    • PUF-based Unique ID
    • PUF-based True Random Number Generator
    • PUF-based Secure Key Storage
    Block Diagram -- PUF-based Hardware Root of Trust
  • tRoot Vx Hardware Secure Modules
    • The Synopsys tRoot Vx HSMs include a highly secure hardware Root of Trust that enables devices to boot securely and permits encryption and decryption of sensitive data allowing it to be stored in non-secure devices or memory. It provides a completely secure environment in a non-secure system from which applications can execute secure cryptographic services.
    • The tRoot Vx HSMs secure SoCs by using unique code protection mechanisms that provide run-time tamper detection and response. Code privacy protection is achieved without the added cost of dedicated secure memory. This unique feature reduces system complexity and cost by allowing the tRoot Vx HSM’s firmware to reside in any non-secure memory space.
    • Commonly, tRoot Vx programs reside in shared system DDR memory. Due to the confidentiality and integrity provisions of the secure instruction controller, this memory is effectively private to the HSM and impervious to attempts to modify it originating in other subsystems in the chip, or from outside. The tRoot Vx HSM’s ROM-less architecture can support system design changes at any time without risk of exposing the system memory to threats and without additional engineering development cost. To minimize the number of attack vectors, tRoot Vx HSMs use a simple interface with a limited set of interactions with the host processor.
×
Semiconductor IP