RISC-V Vector CPU IP
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
- Vector Processing Unit (VPU) boost the performance of AI, AR/VR, computer vision, cryptography, and multimedia processing
- Andes extensions, architected for performance and functionality enhancements
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RISC-V CPU IP
- RISC-V RVA23 Compliant
- >18 SPECint2006/GHz
- 8-wide decode unit
- Advanced branch predictor
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High-performance RISC-V CPU
- Fully compliant with the RVA23 RISC-V specification
- Comparable PPA to Arm Neoverse V3 / Cortex-X4
- Standard AMBA CHI.E coherent interface for SoC and chiplet integration
- Co-architected with Veyron E2 for seamless vector, AI acceleration, and big-little style heterogeneous compute configurations
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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64 bit RISC-V Multicore Processor with 2048-bit VLEN and AMM
- 2 different packages with or without vector: AX46MPV, AX46MP
- in-order dual-issue 8-stage CPU core with up to 2048-bit VLEN
- Symmetric multiprocessing up to 16 cores
- Private Level-2 cache
- Shared L3 cache and coherence support
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32 bit RISC-V Multicore Processor with 256-bit VLEN and AMM
- AndesCore™ A46MP(V) 32-bit multicore CPU IP is an 8-stage superscalar processor with Vector Processing Unit (VPU) based on AndeStar™ V5 architecture and Andes Matrix Multiply (AMM) extension.
- It supports RISC-V standard “G (IMA-FD)”, “ZC” compression, “B” bit manipulation, DSP/SIMD ‘P’ (draft), “V” (vector), CMO (cache management) extensions, Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions.
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All-In-One RISC-V NPU
- Optimized Neural Processing for Next-Generation Machine Learning with High-Efficiency and Scalable AI compute
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High-performance AI dataflow processor with scalable vector compute capabilities
- Matrix Engine
- 4 X-Cores per cluster
- 1 Cluster = 16 TOPS (INT8)
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ARC-V RHX-100 dual-issue, 32-bit single-core RISC-V processor for real-time applications
- High-speed, 32-bit, dual-issue, 10-stage pipeline
- Multicore support for up to 16 CPUs and up to 16 user hardware accelerators per processor cluster
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ARC-V RMX-100 ultra-low power 32-bit RISC-V processor for embedded applications
- 32-bit RISC-V embedded CPU with balanced 3-stage pipeline
- DSP implementation to extend the RISC-V baseline (RMX-100D)
- 2 KB to 64 KB instruction L1 cache
- Up to 2MB instruction and data closely coupled memory (CCM)