Public Key Hardware Accelerator IP
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12
IP
from 6 vendors
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10)
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Hardware accelerator for RSA, DSA, Diffie-Hellman, El-Gamal and Elliptic Curves algorithms
- Direct Memory Access (DMA) and arbiter
- shared memory: no extra silicon cost; inputs and results directly accessible by software
- multiple arithmetic operations: integer multiply, multiply & accumulate, square, addition, subtraction; modular multiplication
- all 32 bits multiple operations up to 8192 bits
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Agile PQC Public Key Accelerator
- Agile IP comprised of HW/FW/SW, adaptable to future standards’ evolution
- Highly configurable IP can be tuned for specific applications with most optimal PPA
- Scalable PQC PKA IP complies with latest NIST PQC algorithms
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Public Key Accelerator
- Modular exponentiation operations with up to 4096-bit modulus
- Prime field ECC operations with up to 571-bit modulus
- Fastest implementation is 58 kGE and 68 Op/s for 2048-bit RSA, 431 Op/s for 1024-bit RSA, 150 Op/s for 384-bit scalar multiplication
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Small RSA/ECC Public Key Accelerators
- The PKA-IP-28 is a family of Public Key Accelerator IP cores designed for full scalability and an optimal “performance over gate count” deployment.
- Proven in silicon, the PKA-IP-28 public key accelerator addresses the unique needs of semiconductor OEMs and provides a reliable and cost-effective solution that is easy to integrate into SoC designs.
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Asymmetric Public Key Cryptography IP
- Constant time of the basic arithmetic unit: protection against timing attacks.
- Regular modular exponentiation (RSA): protection against SPA.
- Regular ECSM: protection against SPA.
- Protection against CPA and collision attacks.
- Protection against Address-bit CPA.
- Protection against fault attacks.
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Blockchain Hardware Accelerator
- Wide variety of ECC curves supported (Weierstrass, Edwards, Montgomery, Twisted-Edwards, …)
- Ideal for FPGA/ASIC integration
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TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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ML-KEM Key Encapsulation IP Core
- The KiviPQC™-KEM IP core is a hardware accelerator for post-quantum cryptographic operations.
- It implements the Module Lattice-based Key Encapsulation Mechanism (ML-KEM), standardized by NIST in FIPS 203.
- This mechanism realizes the appropriate procedures for securely exchanging a shared secret key between two parties that communicate over a public channel using a defined set of rules and parameters.
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GEON™ Secure Boot Hardware Engine
- GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code.
- The security platform employs public-key cryptography (which stores no secret on-chip) to ensure that only unmodified firmware from a trusted source is used by the system.
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Programmable Root of Trust With DPA and FIA for US Defense
- Custom-designed 32-bit secure RISC-V processor
- Multi-layered security model protects all core components against a wide range of attacks
- Security model includes hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
- State-of-the-art DPA resistance, FIA protection and anti-tamper techniques
