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PCIe DMA IP

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Compare 38 IP from 18 vendors (1 - 10)
  • ULL PCIe DMA Controller
    • PCIe Gen 3 (x16)
    • Ultra-fast transfer of data between FPGA logic and memory mapped user space
    • Multi-channel circular buffer architecture
    • Zero-copy circular buffers memory mapped to user space
  • PCIe DMA Controller (Low Latency)
    • Implements standard Transaction layer functions e.g. TLP generation/reception, TLP completion handling and interrupt generation
    • Implements 32-bit, 64-bit, 128-bit and 256-bit User application. (Width selection is based on PCIe endpoint interface width)
    • PCIe Gen1, Gen2 and Gen3 support.
    • Up to 8 independent DMA channels with each channel capable of operating in Block-DMA or Scatter-Gather DMA modes
  • DMA Core for PCIe Hard IP
    • TLP Encoding and Decoding
    • Completion packet handling done by target bridge
    • Integrated Arbiter with round robin fashion
    • 32/64 bit AXI stream user interface from PCIe Hard IP depends on no. of PCIe lanes
    Block Diagram -- DMA Core for PCIe Hard IP
  • DMA for PCI Express (PCIe) Subsystem
    • DMA for PCI Express Subsystem connects to the PCI Express Integrated Block. Both IPs are required to build the PCI Express DMA solution
    • Support for 64, 128, 256, 512-bit datapath for UltraScale+™, UltraScale™ devices.  Support for 64 and 128-bit datapath for Virtex®-7 XT devices
    • Up to 4 host-to-card (H2C/Read) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
    • Up to 4 card-to-host (C2H/Write) data channels for UltraScale+, UltraScale devices. Up to 2 such channels for Virtex-7 XT devices
  • Fibre Channel ASM (Anonymous Subscriber Messaging) Core
    • Message label validation checks performed in hardware
    • Multiple user modes for receiving messages, including strictly mapped message-to-buffer and free-buffer implementations
    • Transmit message chaining options provided
    • Complete set of registers for managing core and configuring core options
    Block Diagram -- Fibre Channel ASM (Anonymous Subscriber Messaging) Core
  • Wrapper IP building blocks for ES1 IP
    • GMII 2 RGMII/SGMII adapter: PHYs and SFPs; built-in MDIO / I2C controller for -PHY
    • Memory protection for high integrity/availability systems: SEC/DED protection of TTE End System Core Memories; built-in self-test of memories; memory scrubbing
    • TTE end system core streaming adapter: Allows interfacing TTE-ES core from user application via packet interface (AXI-S)
    • TTE end system core DMA engine: Support for high latency buses like PCIe while reaching line (1Gbps) throughputs. Customization for any PCIe HARD IP is possible; variant of DMA for SoC use (AMBA interfacing)
  • High Channel Count DMA IP Core for PCI-Express
    • Available for Xilinx or Intel (Altera) Devices
    • User transmits / receives only user data without PCIe protocol
    • AXI standard interfaces for easy integration
    Block Diagram -- High Channel Count DMA IP Core for PCI-Express
  • Multi Channel DMA Flex IP Core for PCI-Express
    • AXI standard interfaces for easy integration
    • User transmits/receives only user data without PCIe protocol
    • All AXI Interfaces have adjustable Datawidth and separate clocking
    Block Diagram -- Multi Channel DMA Flex IP Core for PCI-Express
  • QDMA Subsystem for PCI Express
    • Supports 64, 128, 256 and 512-bit data path
    • Supports x1, x2, x4, x8, or x16 link widths.
    • Supports Gen1, Gen2, and Gen3 link speeds
    • Support for both the AXI4-Memory Mapped and AXI4-Stream interfaces per queue
  • PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
    • Designed to the USB4 Specification v1.0
    • Follows PCIe 1.0 protocol, but can operate at any compatible speed
    • Supports the PCI-SIG Single-Root I/O Virtualization (SR-IOV) Specification
    Block Diagram -- PCIe Controller for USB4 Hosts and Devices supporting PCIe Tunneling, with optional built-in DMA and configurable AMBA AXI interface
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