PCIe 6.0 Controller IP
Filter
Compare
43
IP
from 5 vendors
(1
-
10)
-
PCIe 6.0 Controller EP/RP/DM/SW with AMBA bridge & HPC features, including Arm Confidential Compute Architecture
- Supports all required features of the PCI Express 6.0, 5.0, 4.0, 3.1, 2.1, and 1.1 specifications
-
Configurable controllers for PCIe 6.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
- Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
- Full Transaction Layer, Data Link Layer and Physical Layer
- Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
- Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
-
PCIe 7.0 Controller
- Optimized for high-bandwidth efficiency at data rates up to 128 GT/s
- Separate native TX/RX data path separating posted/Non posted/
- completion traffic
-
CXL 3.0 IP
- Supports CXL 2.0, 1.1, and 1.0 specifications and is compliant with the PCIe 6.0 and offers backward compatibility with PCIe 5.0, 4.0, 3.1, 2.0, and 1.1
-
Supports all key features and performance requirements in the CXL 3.0, 2.0, 1.1 and 1.0 specifications
- Supports key required features of the CXL 3.0 specification and full backwards compatibility with CXL 2.0, 1.0 and 1.1
- Supports PCIe 6.0 mode with 64 GT/s and x16 link width
- CXL license includes PCIe 6.0 functionality and fallback mode
- Customers using CXL do not need an additional PCIe 6.0 license
-
PCIe 6.0 PHY in Samsung (SF5A, SF4X, SF2)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
- Supports PCIe Lane Margining at Receiver
- Spread-spectrum clocking (SSC)
-
PCIe 6.0 PHY in TSMC (N6, N5, N4P, N3P, N3E)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
- Supports PCIe Lane Margining at Receiver
- Spread-spectrum clocking (SSC)
-
PCIe 6.0 PHY NCS IP for TSMC (N3E, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Supports PCIe 6.0, encoding, backchannel initialization
- Supports PCIe Lane Margining at Receiver
- Spread-spectrum clocking (SSC)
-
PCIe 6.x / PCIe5.x / PCIe4.x / PCIe3.x / PCIe2.x / PCIe1.x Controller
- Implements PCIe 6.0 Specification at 64 GT/s
- Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
- Designed for easy integration with Alphawave PipeCORE™ PCIe PHY IP
- Key IP features configurable to optimize IP for exact application requirements
-
112G LR-Max Ethernet PHY for TSMC N5
- Supports 1.25 to 112 Gbps data-rate
- Supports PCI Express 6.0, 1G to 400G/800G Ethernet, CCIX, CXL, JESD204C, CPRI, SATA, and OIF CEI LR/MR/VSR Electrical Interfaces protocols