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PCIe 6 IP

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Compare 258 IP from 35 vendors (1 - 10)
  • PCIe Gen 6 SERDES IP - supports up to 112G LR ethernet with low power and latency
    • PCie Gen 5/6 compliant
    • Up to 112G PAM 4 support
    • less than 6 pj/bit typical power consumption
  • PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge and LTI & MSI Interfaces
  • PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller with AMBA bridge
  • PCIe 6.0 (Gen6) Premium Controller
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- PCIe 6.0 (Gen6) Premium Controller
  • Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
    • Supports all required features of the PCI Express 6.2/6.1/6.0.1 (64GT/s), 5.0 (32 GT/s), 4.0 (16 GT/s), 3.1 (8 GT/s) and PIPE (32-bit) specifications
    • Based on silicon-proven PCIe 6.x controller design
    • Allows a full 64GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    Block Diagram -- Adds security Interfaces, features to PCIe 6.0 Premium controllers (Gen6)
  • PCIe 6.0 Integrity and Data Encryption Security Module
    • Compliant with PCI Express IDE specification
    • Support for TDISP
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP packet-based interface
    • FLIT mode support
    Block Diagram -- PCIe 6.0 Integrity and Data Encryption Security Module
  • PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
    • Supports the latest features of PCIe 6.x and CXL 3.x specifications
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Delivers more power efficiency across channels with unique DSP algorithms
    • Enables near zero link downtime with patent-pending diagnostic features
    Block Diagram -- PCIe 6.0 PHY, TSMC N6 x2 1.2V, North/South (vertical) poly orientation
  • PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
    • Supports the latest features of PCIe 6.x and CXL 3.x specifications
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Delivers more power efficiency across channels with unique DSP algorithms
    • Enables near zero link downtime with patent-pending diagnostic features
    Block Diagram -- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
  • PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
    • Supports the latest features of PCIe 6.x and CXL 3.x specifications
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Delivers more power efficiency across channels with unique DSP algorithms
    • Enables near zero link downtime with patent-pending diagnostic features
    Block Diagram -- PCIe 6.0 PHY, TSMC N4P x4, North/South (vertical) poly orientation
  • PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
    • Supports the latest features of PCIe 6.x and CXL 3.x specifications
    • Supports PAM-4 signaling and up to x16 lane configurations with bifurcation
    • Delivers more power efficiency across channels with unique DSP algorithms
    • Enables near zero link downtime with patent-pending diagnostic features
    Block Diagram -- PCIe 6.0 PHY, SS SF5A x4, North/South (vertical) poly orientation
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