IP Catalog > PCIe 4.0 PHY TSMC 16FF+

PCIe 4.0 PHY TSMC 16FF+ IP

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Compare 8 IP from 3 vendors (1 - 8)
  • PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
  • PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 16FFC, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x1-lane, RC/EP, TSMC 16FFC, N/S orientation
  • PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 16FFC, N/S orientation
    • Fully compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base 1.1 electrical specifications
    • Compliant with PIPE4.4.1 (PCIe) specification
    • Supports all power saving modes (P0, P0s, P1, P2) defined in PIPE4.4.1 specification
    • Supports L1 PM Substates with CLKREQ#
    Block Diagram -- PCIe Gen4 PHY, x4-lane, RC/EP, TSMC 16FFC, N/S orientation
  • 25G PHY, TSMC 16FFPGL x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 16FFPGL x4 North/South (vertical) poly orientation
  • 25G PHY, TSMC 16FFC x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 16FFC x4 North/South (vertical) poly orientation
  • 25G PHY, TSMC 16FFC x1 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 16FFC x1 North/South (vertical) poly orientation
  • 25G MR Ethernet PHY, TSMC 16FFC x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G MR Ethernet PHY, TSMC 16FFC x4 North/South (vertical) poly orientation
  • 25G MR Ethernet PHY, TSMC 16FFC x1 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G MR Ethernet PHY, TSMC 16FFC x1 North/South (vertical) poly orientation
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