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PCI Express Gen3 IP

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Search (36)
Compare 36 IP from 6 vendors (1 - 10)
  • PCI Express Gen3 SERDES PHY on TSMC CLN40G
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.107 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.9 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 36mW per lane at 8Gbps (4.5mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.1 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen3 SERDES PHY on Samsung 28LPP
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.134 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 7.0 mW/Gbps including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3 / SATA3 SERDES PHY on Samsung 28FDSOI
    • Programmable SERDES analog front end that supports 1 to 8 Gbps standard serial protocols
    • Compact form factor – 0.165 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.5 mW/Gbps including termination
    • Finely configurable receiver impedance, CTLE gain and bandwidth, with fully adaptive CTLE and DFE
  • AXI Bridge for PCI Express (PCIe) Gen3 Subsystem
    • Maximum Payload Size (MPS) up to 256 Bytes
    • Messaged Signaled Interrupt (MSI)
    • Memory mapped AXI4 access to PCIe space
    • PCIe access to memory mapped AXI4 space
  • UltraScale Gen3 Integrated Block for PCI Express (PCIe)
    • High Peformance and High Bandwidth Applications
    • Compute and Data Co-processing Applications
    • Medical Imaging, High-Performance Computing & Communications Packet Processing
  • Virtex-7 FPGA Gen3 Integrated Block for PCI Express (PCIe)
    • Compliant with the PCI Express Base Specification 3.0
    • Supported Lane width: x1, x2, x4 and x8
    • Fully compliant with PCI Express transaction ordering rules
    • Optimal buffering for high bandwidth Direct Memory Access (DMA) applications
  • PCI Express Gen3/Enterprise Class SERDES PHY on Samsung 28LPP
    • Industry leading low power PMA macro – 88mW per lane at 8Gbps (11.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.216 mm2 active silicon area per lane including ESD
    • Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.266 mm2 active silicon area per lane including ESD
    • Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • QDMA Subsystem for PCI Express
    • Supports 64, 128, 256 and 512-bit data path
    • Supports x1, x2, x4, x8, or x16 link widths.
    • Supports Gen1, Gen2, and Gen3 link speeds
    • Support for both the AXI4-Memory Mapped and AXI4-Stream interfaces per queue
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