Nonvolatile Memory IP
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Multiple - Time Programmable Non-Volatile Memory
- Density : 8bits ~ 1024Kbits
- Read voltage : low to 1.0V (LV)
- Write mode : Byte / Word write
- Read mode : Byte / Word read
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On-chip Nonvolatile APB Memory Controller
- Fully AMBA 2 APB-compliant
- Compatible with AMBA 3 APB
- Multiple memory sizes and variable number of NVM blocks
- Configurable 8-, 16-, or 32-bit data bus size
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On-chip Nonvolatile AHB Memory Controller
- Provides an Industry-Standard Software Interface to Microsemi Fusion Flash Memory
- Implements a Subset of the Common Flash Memory Interface Specification Release 2.0
- Implements Standard Slave AHB Bus Hardware Interface
- Supports Read, Automatic Write and Erase, and Status Operations
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LPDDR5X Secondary/Slave (memory side!) PHY
- JEDEC standard LPDDR5X @ 8533Mbps (Mbits per second per pin)
- Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
- Support for byte-mode DRAM devices for high capacity systems
- ZQ Calibration
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LPDDR5 Secondary/Slave (memory side!) PHY
- JEDEC standard LPDDR5 @ 6400 Mb per second per pin.
- Flexible channel architecture – 16- or 32-bit data path widths, supporting either single x32 channel or two x16 channels – 64-bit support, supporting two x32 channels
- Support for byte-mode DRAM devices for high capacity systems
- ZQ Calibration
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LPDDR4x Secondary/Slave (memory side!) PHY
- JEDEC standard LPDDR4X @ 4267 Mb per second per pin.
- Flexible channel architecture
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LPDDR4x/5 Secondary/Slave (memory side!) PHY
- Supports JEDEC standard LPDDR5, LPDDR4X, LPDDR4
- Secondary side PHY
- Custom implementations available
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ReRAM as FTP/OTP Memory
- Non-volatile Memory Flexibility
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Spin Orbit Torque Magnetic Random-Access Memory
- With the advent of mobile and handheld electronic devices, the demand for much smaller, faster and ultra-low power systems keeps growing. Yet to meet such needs, the microelectronics industry cannot rely anymore on following Moore’s law like it has for the last decades.
- Embedded memories, which represent a major part of the circuits silicon area have now become a major contributor to power dissipation in integrated system circuits. To solve these issues, several technologies are intensively investigated to replace existing embedded memories (SRAM and Flash).
- Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) has been chosen by the industry as the non-volatile memory technology of choice to replace Embedded Flash at advanced technology nodes.
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55nmHV MTP Non Volatile Memory for Standard CMOS Logic Process
- 1K-Time Programmable (MTP)
- > 10 years retention
- Uses standard CMOS process with no additional masks