Lightweight Multi-Format Video Encoder IP
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Lightweight and Configurable Root-of-Trust Soft IP
- QRoot Lite™ is a silicon IP solution designed specifically for resource-constrained MCUs and IoT devices. It provides essential security capabilities including secure boot, device attestation, and sealed storage.
- Built on the industry-standard TCG MARS specification, QRoot Lite™ simplifies integration, reduces costs, and accelerates your journey toward regulatory compliance and trusted embedded products.
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NIST’s ASCON Lightweight Crypto Algorithm Accelerator
- The ASCON-IP-41 is an efficient implementation of NIST’s lightweight crypto algorithm family ASCON. ASCON is a single algorithm defined in different modes to support AEAD and HASH operations.
- As a multi-purpose algorithm with minimal area requirements ASCON is extremely suitable for low-cost and low-power applications.
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Cryptographic co-processor for lightweight cryptography
- Support AES-XTS mode — IEEE Std 1619-2007 standard compliance
- Support 128 and 256-bit key size
- Random memory block access support
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Ascon, A Lightweight Cryptographic Suite for AEAD and Hashing
- Small Resource Requirements
- Versatile Algorithm Support
- Secure Architecture
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SDI Mapper for TICO-RDD35 & TicoXS (JPEGXS) lightweight codecs
- Manage both the TX & RX
- Manage the insertion of the TICO-RDD35 or JPEG-XS detection box over the active area of the SDI
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TICO Lightweight HD Encoder
- Visually Lossless quality up to 4:1
- 4:2:2 ; 4;4:4 & 8,10,12bit
- CBR (VBR as option)
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TICO Lightweight HD Decoder
- Visually Lossless quality up to 4:1
- 4:2:2 ; 4;4:4 & 8,10,12bit
- CBR (VBR as option)
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Lightweight Configurable Display Controller
- Fully programmable clock and timing control for flat panel displays with progressive scanning
- Support for resolutions up to 4096×4096
- Completely variable timing parametersfor standard or specific display resolutions
- Support for 8,1618 or 24 bit RGB output color depth
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Low power 32-bit processor with lightweight computing power
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 3 to 4-stage variable length pipeline;
- General register: 32 32-bit GPRs;
- Bus interface: Tri-bus (instruction bus + data bus + system bus);
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AVSBus v1.4.1 Verification IP
- The AVSBus Verification IP provides an effective and efficient way to verify the components interfacing with AVSBus interface of an IP and SOC.
- The AVSBus VIP is fully compliant to PMBus part III - AVSBus Specification version 1.4.1.
- The VIP is lightweight with an easy plug-and-play interface, so that there is no hit on the design cycle time.