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LPDDR Memory IP

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Compare 155 IP from 16 vendors (1 - 10)
  • LPDDR Memory Model
    • Supports LPDDR memory devices from all leading vendors.
    • Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1.
    • Supports all the LPDDR commands as per the specs.
    • Supports up to 2GB device density
    Block Diagram -- LPDDR Memory Model
  • LPDDR4/4x/5/5x PHY
    • Supports JEDEC SDRAM standards including LPDDR4 (1.1V), LPDDR4x (0.6V), LPDDR5/5x (0.5V)
    • Supports data rates up to 4,266 Mbps LPDDR4/LPDDR5 and up to 8,533 Mbps LPDDR5x
    • Support for 16, 32 and 64-bit operation
    Block Diagram -- LPDDR4/4x/5/5x PHY
  • High-Performance Memory Expansion IP for AI Accelerators
    • Expand Effective HBM Capacity by up to 50%
    • Enhance AI Accelerator Throughput
    • Boost Effective HBM Bandwidth
    • Integrated Address Translation and memory management:
    Block Diagram -- High-Performance Memory Expansion IP for AI Accelerators
  • LPDDR Assertion IP
    • Specification Compliance
    • Supports all signal level checks including X detection
    • Supports LPDDR memory devices from all leading vendors.
    • Supports 100% of LPDDR protocol standard JESD209B and JESD209A-1.
    Block Diagram -- LPDDR Assertion IP
  • LPDDR4X Verification IP
    • Compliant with JEDEC LPDDR4X Specification version JESD209-4-1.
    • Supports LPDDR4X memory devices from all leading vendors.
    • Supports multiple densities: 4Gb to 32Gb.
    • Supports all lpddr4x ODT CA/CS/CKT control via MRS register
    Block Diagram -- LPDDR4X Verification IP
  • LPDDR Controller
    • Memory controller interface complies with DFI standard up to 5.0
    • Application-optimized configurations for fast time to delivery and lower risk
    • Sideband and in-line SEC/DED ECC
    • Supports advanced RAS features including error scrubbing, parity, etc.
    • Compliant to LPDDR5/4X/4/3 protocol memories
    • Priority per command on Arm®AMBA® 4 AXI, AMBA 3 AXI
  • DDR and LPDDR Combo PHY
    • Supports multiple combinations of DDR/LPDDR interfaces
    • Compliant with JEDEC DDR and LPDDR standards
    • Supports all auto calibrations
    • Industry leading area and power
  • LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
    • Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
  • LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
    • Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
  • LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
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