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Search (16)
Compare 16 IP from 6 vendors (1 - 10)
  • Linear Regulator, Low-noise optimized for sensitive application such as RF or PLL blocks
    • Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
    • Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
    • Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
    • Cost efficient solution compared to external Power Management.
    Block Diagram -- Linear Regulator, Low-noise optimized for sensitive application such as RF or PLL blocks
  • Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
    • Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
    • Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
    • Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
    • Cost efficient solution compared to external Power Management.
    Block Diagram -- Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
  • Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
    • Starring a PSRR of -65 dB at 20 kHz and a low intrinsic noise, combined with a low quiescent current of 110 uA, the nLR-VAIPO helps optimize the power management network for audio handheld applications such as smartphone and tablet.
    • Small footprint: only 0.12 mm2 (including bandgap reference and POK circuit)
    • Minimization of the overall system power, through the support of 3 modes of operation: normal, shutdown and bypass
    • Eases integration in SoC nLR-VAIPO is delivered with behavioral models. These new views enable to build an optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation.
    Block Diagram -- Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
  • Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
    • Starring a PSRR of -65 dB at 20 kHz and a low intrinsic noise, combined with a low quiescent current of 110 uA, the nLR-VAIPO helps optimize the power management network for audio handheld applications such as smartphone and tablet.
    • Small footprint: only 0.12 mm2 (including bandgap reference and POK circuit)
    • Minimization of the overall system power, through the support of 3 modes of operation: normal, shutdown and bypass
    • Eases integration in SoC nLR-VAIPO is delivered with behavioral models. These new views enable to build an optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation.
    Block Diagram -- Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
  • RadHard Wideband SiGe VCO for Low Ultra Low Noise Application
    • 0.9 GHz - 3.5 GHz VCO with with 2 GHz Phase Noise less than –114 dBc/Hz @ 100 kHz.
    • Single power supply of 5.0 V. Integrated bandgap reference and LDOs with power down mode.
    Block Diagram -- RadHard Wideband SiGe VCO for Low Ultra Low Noise Application
  • Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
    • Low noise: high power Supply Rejection Ratio (PSRR): - 65 dB at F < 10 kHz
    • Low intrinsic noise: 20 uVRMS at 10 Hz to 20 kHz
    • Low Bill-of-Material: optimized in density for the best trade-off for the given output current and input voltage range
    • Cost efficient solution compared to external Power Management.
    Block Diagram -- Linear Regulator, Low Noise optimized for sensitive application such as RF or PLL blocks
  • MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in GF 55LP
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 40LP
  • MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in TSMC 16FFC
  • MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
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