IP Catalog > Inline Memory Encryption (IME) Engine

Inline Memory Encryption (IME) Engine IP

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  • Inline memory encryption engine, for FPGA
    • Performs encryption, decryption and/or authentication using AES Counter Mode (CTR) or Galois Counter Mode (GCM)
    • Supports AES key sizes 128 or 256
    • Internal key management with NIST-compliant key generation
    • Encrypt memory space into user-defined vaults, each with a unique key
    • Compatible with AMBA AXI4 interface
    • Supports hard or soft memory controllers in Xilinx FPGA and SoC devices
    • Supports multiprocessor systems
    Block Diagram -- Inline memory encryption engine, for FPGA
  • Inline cipher engine with AXI, for memory encryption
    • Throughput: 128 bit (16 Byte) wide encryption/decryption per cycle
    • Throughput: 1 tweak computation per 4 clock cycles
    • Bidirectional design including arbitration between read and write requests
    • Zero clock overhead for switching between encryption (write) and decryption (read)
    • 30-40 cycle data channel latency
    Block Diagram -- Inline cipher engine with AXI, for memory encryption
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