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Inline Memory Encryption (IME) Engine IP

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  • Inline Memory Encryption (IME) Security Module - for DDR/LPDDR
    • Data confidentiality with independent cryptographic support for read & write channels
    • Standards compliant: NIST SP800-38E, IEEE Std. 1619-2018
    • FIPS 140-3 certification support
    • Per region protection (index or address based)
    Block Diagram -- Inline Memory Encryption (IME) Security Module - for DDR/LPDDR
  • LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
    • Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5, LPDDR4, and LPDDR4X
  • LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
    • Supports JEDEC standard LPDDR5, LPDDR4, and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5/4/4X PHY and other LPDDR5/4/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5, LPDDR4 and LPDDR4X with Advanced Features Package
  • LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5X, LPDDR5, and LPDDR4X
  • LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
    • Supports JEDEC standard LPDDR5X, LPDDR5 and LPDDR4X SDRAMs
    • Multiport Arm® AMBA® interface (AXI™4 / AXI™ 3) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys LPDDR5X/5/4X PHY and other LPDDR5X/5/4X PHYs
    • Best-in-class performance with unique features such as QoS-based scheduling, inline ECC, and dual-channel support
    Block Diagram -- LPDDR Controller supporting LPDDR5X, LPDDR5 and LPDDR4X with Advanced Features Package
  • DDR Secure Controller supporting DDR5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Secure Controller supporting DDR5
  • DDR Low Latency Controller supporting DDR5
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Low Latency Controller supporting DDR5
  • DDR Controller supporting DDR5 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 with Advanced Features Package
  • DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 with a CHI interface and Advanced Feature Package
  • DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs and DIMMs
    • Multiport Arm® AMBA® interface (4 AXI™/3 AXI™) with managed QoS or single-port host interface to the DDR controller
    • DFI 5.0 compliant interface to Synopsys DDR5/4 PHY or other DDR5/4 PHYs
    • Best in class performance with unique features such as QoS-based scheduling and phase-aware scheduling
    Block Diagram -- DDR Controller supporting DDR5 MRDIMM Gen2 with Advanced Features Package
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